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Designing with Xilinx Virtex: Technical Details
Course Summary
Virtex Technology Family In Depth
A detailed description of the Virtex-E and Virtex-II technology resources, and the advanced
features available in the ISE design tools to make the most efficient use of these resources.
“Front to Back” Design Methodology Description
From RTL code to fully implemented design, including use of sophisticated synthesis constraints;
Xilinx behavioural and gate level simulation libraries; Core Generator; multi-clock domain timing
analysis; floor planning; power estimation and Multipass Place and Route.
Language-Specific Optimisations for Xilinx
VHDL and Verilog coding styles to achieve optimal synthesis results; accessing Virtex device resources with VHDL and Verilog;
FSM and data-path optimisation; and tracing gate level timing violations back to source code.
Course Agenda
Day 1:
- Virtex family architecture and features
- Configurable Logic Block (CLB)
- Slice structure
- SRL16E shift register
- Memory and multipliers
- Clock resources
- Input Output Block (IOB)
- SelectRAM
- Select I/O features in Virtex-E/II
- Double Data Rate (DDR) registers
- Digital Controlled Impedance (DCI)
- Low Voltage Differential Signalling (LVDS)
- Virtex routing resources
- Clock buffers, buses and interconnect
- Floorplan Viewer/ FPGA Editor
- Xilinx design flow overview
Day 2:
- ADigital Clock Manager (DCM) features
- Delay Locked Loop (DLL)
- Digital Frequency Synthesiser (DFS)
- Digital Phase Shifter (DPS
- Digital Spread Spectrum (DSS)
- Advanced timing analysis in ISE
- Timing constraints
- Single clock timing analysis
- Multi-clock domain timing analysis
- Improving quality of results
- Re-entrant routing
- Multipass Place and Route (MPRR)
- Xilinx Core Generator
- Core Generator in a HDL design flow
- Simulating Core Generator components
- PCB layout considerations
- Configuration
Day 3:
- Review of RTL coding guidelines
- Accessing Virtex device resources from HDL
- Resets and clock enables
- Bi-directional I/O
- Issues with resets
- Language specific optimisations
- Architectural optimisations
- Finite State Machine (FSM) optimisations
- Power estimation
- Gate level simulation
- VITAL libraries
- SDF annotation
- Simulation issues
Workshop Labs
The lab exercises demonstrate how the design flow is
used in real life design situations. Delegates will experience the entire
design flow in detail, through RTL simulation; synthesis; Place and Route;
timing analysis and gate level simulation. The labs concentrate on how to use
the tools effectively rather than writing source code.
The lab sessions include
- Use of Core Generator and Unified Library components:
DCM’s Double Data Rate I/O’s, etc
- Advanced multi-clock domain timing analysis
- Improving Fmax and device utilization
- Using Multi-Pass Place and Route.
- Applying effective synthesis constraints
- Tracing and fixing timing violations
- Understanding how to use Xilinx simulation libraries
- Clock domain synchronization
- Using the floorplan tool
Course OverView
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