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SystemC Verification (SCV) Library
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Free WebSeminar |
| SystemC is increasing being adopted for the verification of VHDL and Verilog designs and systems.
However SystemC lacks some essential features for applying proven verification techniques such as randomization,
Transaction Level Modeling (TLM) and dynamic resource allocation. The new SystemC Verification (SCV) and Cadence Verification Extension (CVE)
libraries have been design to address this need. This web seminar will illustrate the advantages
of the SCV and CVE SystemC extensions for verification.
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| Transaction Level Assertions with PSL
| Free WebSeminar |
Assertions and embedded functional checks are proven verification aids
and have been used for years by HDL designers. However the VHDL assertion statement, and ad-hoc uses of $display in Verilog,
are not powerful enough to describe the typical multi-cycle design property we wish to check.
The
Property Specification Language (PSL) combines familiar HDL boolean expressions with effective operators and
dedicated verification constructs to easily and concisely describe complex design properties. In this web seminar, we will
describe how to create PSL assertions for complex interface protocols using a Transaction Level Modeling (TLM) approach.
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