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Verilog Application Workshop : Overview & Booking
Overview
A worldwide industry standard, the Esperan Verilog Application Workshop
provides a thorough background in the use and application of Verilog to digital hardware
design. This total training package covers all aspects of the language: from basic
concepts and syntax, through synthesis coding styles and guidelines, to advanced
language constructs and design verification.
Latest Updates 2007
Now with extra Verilog2001 content and an overview of SystemVerilog
Duration
The workshop is based around a 5-day agenda. This can also be taken in two stages
by splitting the agenda into separate 2-day Introduction and 3-day Advanced modules.
We can also offer standard or customized versions of this workshop onsite or at the location of your choice.
Objectives
- To provide a complete understanding of the essential concepts of Verilog.
- To give you practical experience of writing Verilog for synthesis and verification in a
project-based environment using the latest tools.
- To give you the knowledge to approach your Verilog design project with
confidence.
Prerequisites
Delegates should have a basic knowledge of digital hardware design and be
familiar with their choice of operating system. The workshop assumes no prior
knowledge of Verilog.
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VERILOG APPLICATION WORKSHOP |
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