Language Basics
Language concepts and constructs, including use of register versus wire types; blocking and nonblocking assignment and case statement issues.
Synthesis Coding Styles
Verilog templates for inferring combinational and registered logic, and a thorough explanation of the rules for writing high quality, reusable RTL.
Advanced Constructs and Verification Issues
Use of subprograms, compiler directives and system tasks and functions. Language techniques for testbench design are also covered.

Workshop Agenda

• Verilog language introduction
• Modules; creating hierarchy; procedures; compilation; comments; identifier rules
• Data-types and Logic System
• Logic value system; data types; vectors; literals; net and register types; parameters; arrays
• Verilog Operators
• Introduction to Verilog operators.
• Procedural and Continuous Statements
• Inital and always; procedural assignment; event control; if and case(x|z); loops; continuous assignments; multiple continuous and procedural assignments
• Procedural Statements and the Simulation Cycle
• Blocking and non-blocking assignment; simulation cycle summary; event, wait and delay based timing control; timescale directive; simulation race conditions.
• Blocking and Non-Blocking Statements
• Issues and guidelines for use of blocking/non-blocking in registered and combinational logic
• Verilog Sample Design
• Creating and verifying an RTL design.
• RTL Rules and Guidelines
• Rules for describing combinational and registered logic in Verilog; Blocking assignment in clocked procedures
• Synthesis Coding Styles
• State machine description; if and case synthesis; parallel and full case; synthesis directives; initial blocks; unsupported constructs; register and latch inference issues; tri-state inference
• Tasks and Functions
• Function declaration and call; task declaration and call; task issues;
• System Control
• Compiler directives; system tasks and functions
• Using a Verilog Test Bench
• Simple stimulus; fork and join; events; vector capture and playback; clock generation

The lab sessions include

• Familiarization with simulation and synthesis tools
• Describing and verifying combinatorial logic
• Creating registered logic
• Using vector arithmetic packages
• Structural design and hierarchy
• Verification using visualization of results
• State machine design
• Verification using script driven, self-checking testbenches
• Integration and verification of a third-party IP model