Modports allow direction information to be specified for signals declared in SystemVerilog interfaces. By connecting to an interface via a modport, a module inherits information about the direction of a signal, i.e. whether it is an input, output or bidirectional inout. Modports can also be used to conceal signals from modules, to prevent access.

If you are unfamiliar with SystemVerilog, please see the SystemVerilog Interfaces tutorial first.

A simple interface does not contain any direction information for the interface signals. Therefore a module to which the interface is connected could read or write any interface signal. Typically a bus connection between two modules will have a direction associated with it, there will be a transmitter or master to send data over the connection, and a receiver or slave to read the information. This gives us two views of the bus connection. You can define these views using interface modports.

An interface can have any number of modports, and each can define a different view of the interface contents. A modport can also define a subset of the interface contents to restrict access to these contents.

Consider the following example:-

interface mod_if;
  logic a, b, c, d;
  modport master (input a,b, output c,d);
  modport slave (output a,b, input c,d);
  modport subset (output a, input b);
endinterface

This example provides a modport named master through which a module reads signals a and b and writes signals c and d, and provides another modport, slave, for exactly the opposite use.

There is also a modport subset, which only allows access to signal a as an output and b as an input.
 

Selecting a Modport.

You can select an interface modport in your module declaration port list:

module master_mod (mod_if.master mbus);
...
endmodule

module slave_mod (mod_if.slave sbus);
   ...
endmodule

module testbench;

   mod_if busA();

   master_mod mmod (.mbus(busA));

   slave_mod smod (.sbus(busA));

endmodule

Or you can select the interface modport in your module instance port map:
 

module master_mod (mod_if mbus);
   ...
endmodule

module slave_mod (mod_if.slave sbus);
   ...
endmodule

module testbench;

   mod_if busA();

   master_mod mmod (.mbus(busA.master));

   slave_mod smod (.sbus(busA.slave));

endmodule

Or, for readability, you can use both methods, assuming they match.

If you select a modport which defines a subset of signals, then any attempt to access signals outside that subset should give you elaboration errors:

module subset_mod (mod_if.subset ifport);
   ...
   assign ifport.c = 1`b1; // ERROR
   ...
endmodule

Issues with Modports.

Just because you declared modports in an interface, does not mean a designer has to use them. They can ignore the modports and connect just to the interface.

Also even if a designer does connect to an interface via a modport, it still does not prevent a designer from writing to an input signal and reading from an output signal. After all, you can write to input ports and read from output ports in standard Verilog.

So although interface modports are very useful for specifying design intent and documenting interfaces, they do not provide any additional error checking.