Esperan - VHDL Application Workshop : Agenda


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VHDL Application Workshop : Technical Details

Overview & booking

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Course Structure
The workshop is based around a 5-day agenda. This can also be taken in two stages by splitting the agenda into separate 2-day Introduction and 3-day Advanced modules.

Course Summary

Language Basics
The first two days of the course cover the fundamental principles of the language and the constructs most commonly used in synthesisable Register Transfer Level (RTL) design.
Synthesis Coding Styles
The third day examines synthesis coding styles and guidelines in depth, including a thorough explanation of the rules for writing high quality, reusable syntheizable code.
Advanced Constructs and Verification Issues
Days four and five introduce further language constructs and consider techniques and strategies for the functional verification of large scale designs.

Workshop Agenda

Days 1-2 Language Basics and Application Overview

VHDL application overview
VHDL language introduction

Design units and main language concepts

Signals and drivers
Pre-defined and user defined types
Standard logic
Array, enumerated and record types

Logical and relational operators, concatenation and array slices
Processes and sequential statements
Concurrent statements and equivalent processes
Simulation execution, sensitivity lists and wait statements
Variables and variable use
Arithmetical operators, overloading and arithmetic packages

Overview of coding styles for testbenches, RTL and behavioral code

Datapath and control examples of behavioral and RTL modeling

The synthesis process and methodology overview

Day 3: Synthesis Coding Styles in Depth

RTL coding styles and guidelines for efficient synthesis

Describing combinatorial logic
Inferring registered logic

Simulation, synthesis and optimization of arithmetic operators
Coding styles for efficient hardware synthesis
FSM´s and state vector encoding
Synthesis of variables
Modeling timing in VHDL

Delay modeling, gate level simulation and VITAL

Day 4-5: Language Constructs, Coding Styles & Strategies for Verification

Procedures and functions

Overloading,type qualification and resolution functions

Generics, generates and blocks
Unconstrained, type indexed and multi-dimensional arrays
Types, sub-types, closely-related types and type conversions
Coding styles and strategies for generating test stimulus
Creating clocks and resets

Reading and writing data using file I/O
Script driven testbenches
Data and message outputs for efficient verification
Result visualization

Design organization and management

Options and strategies for using configurations
Compilation, elaboration, initialization and simulation
Efficient use of packages

VHDL2006 Updates

New operators
Statement enhancements
Array declarations and assignments
Sized and signed literals
New verification features
Property Specification Language (PSL) assertions
Fixed/floating-point arithmetic packages

Appendices

Index of code examples
Introduction to Property Specification Language (PSL)
Index

Workshop Labs
The labs have been designed to follow on from each other over the course of the workshop, building on code developed in each lab to create an overall design project.
The first few labs get you familiar with the tools you are using and the basic steps involved in simulating and synthesizing a small design. Subsequent labs are based upon design modeling and verification issues that are typically encountered in a real world design project.

The lab sessions include

Familiarization with simulation and synthesis tools
Describing and verifying combinatorial logic
Creating registered logic
Using vector arithmetic packages
Structural design and hierarchy
Verification using visualization of results
State machine design
Verification using script driven, self-checking testbenches
Integration and verification of a third-party IP model

Overview & booking

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