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VHDL for Verilog Engineers - Overview & Booking
Overview
There is increasing pressure on Hardware Designers to become bi-lingual. Design
reuse, commercial Intellectual Property and distributed design teams are creating
language neutral design methodologies, where an engineer may use VHDL for writing
testbenches; Verilog and VHDL for RTL design and Verilog for gate level simulation.
VHDL for Verilog is an intensive course in VHDL for engineers who already have experience of
Verilog. Based on Esperan's high-quality VHDL Application Workshop and delivered by
trainers especially chosen for their in-depth knowledge of both languages, this course is
the fastest and most effective method for Verilog engineers to
understand the intricacies of VHDL and become proficient in the language.
Duration
The workshop is based around a 3-day agenda, covering language basics; synthesis
coding styles and testbench creation.
We can also offer standard or customized versions of this workshop onsite or at the location of your choice.
Objectives
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To provide a complete understanding of the essential concepts of VHDL
and how these differ from Verilog. |
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To give you practical experience of writing VHDL for synthesis and verification. |
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To give you the knowledge to approach your VHDL or dual language design project with
confidence. |
Prerequisites
This workshop assumes prior knowledge of Verilog, for example from attendence at Esperan's Verilog Application workshop.
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VHDL FOR VERILOG ENGINEERS |
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