Esperan - VHDL for Verilog Engineers Training : Agenda


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VHDL for Verilog Engineers - Technical Details

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Course Summary
Verilog and VHDL are close enough to be familiar, but can be frustratingly different in the detail. This course will explain the key language differences. For example, in VHDL:

Both concurrent and procedural assignments can be made to the same object.
Different objects are needed for the targets of blocking and non-blocking assignments.
Case statements must be full and parallel by design.
There are 9 logic values, but they are not part of the main VHDL standard! Neither are arithmetic operators for vectors!

This course covers:-

Language Basics
Language concepts and constructs, including use of high level data-types; issues with arithmetic operators and use of signals versus variables.
Synthesis Coding Styles
VHDL templates for inferring combinational and registered logic, and a thorough explanation of the rules for writing high quality, reusable RTL.
Advanced Constructs and Verification Issues
Use of subprograms and advanced constructs such as generics and generates. Language techniques for testbench design are also covered, including File IO.

Workshop Agenda

VHDL language introduction

Entity; architecture; hierarchy; configurations; processes; types; packages; libraries; comments; compilation order; language rules.

Signals and Data-types

Types; signal assignments; arrays; records; logic value sets.

VHDL Operators

Logical and relational operators; concatenation; array slices.

Sequential Statements

Process; if and case syntax; for loops; Multiple concurrent & sequential assignment statements; conditional and selected signal assignment.

Sequential Statements and the Simulation Cycle

Simulation cycle; wait statement; variables; loops

Arithmetic Operators

Operators; vendor arithmetic packages

Definition of RTL Code

Rules for describing combinational and registered logic in VHDL

Synthesis Coding Styles

State machine descriptions; if and case synthesis; initialization

Advanced Synthesis Coding Styles

Synthesis of variables; state vector encoding; synthesis directives; tri-states

Functions & Procedures

Function declaration and call; procedure declaration and call; parameter classes and modes; type qualification; resolution functions

Advanced Concurrent VHDL

Generics; generates

Advanced Data Types

Multi-dimensional arrays; type conversion and closely related types; subtypes; aliases

Testbench Coding Styles

Simple stimulus; assertions; clocks and resets; textio; pseudo-code based example

Workshop Labs
The labs have been designed to follow on from each other over the course of the workshop, building on code developed in each lab to create an overall design project.

The lab sessions include

Familiarization with simulation and synthesis tools
Describing and verifying combinatorial logic
Creating registered logic
Using vector arithmetic packages
Structural design and hierarchy
Verification using visualization of results
State machine design
Verification using script driven, self-checking testbenches
Integration and verification of a third-party IP model

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		Esperan has been providing VHDL training and Verilog training in UK, US, Canada, Western Europe, South Africa and throughout the world.

Esperan contact information	US contact information
Phone +44 1344 865436 Fax +44 1344 865347 Email info@esperan.com	Tollfree Tel. 1800 220 8148 Fax. 1888 641 6431 Email US-sales@esperan.com