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NEW! Verification with VHDL : Overview & Booking
Overview
As ASIC and FPGA designs grow in complexity, verification is becoming the greatest
challenge for completing design projects on time. To address this challenge, designers
must make the most of VHDL’s capabilities, as well as adopting verification
techniques such as Transaction Level Modeling (TLM) and Assertion Based Verification
(ABV).
Esperan’s Verification with VHDL course describes specialized VHDL techniques
for verification; explores essential verification technologies such as TLM and ABV;
introduces complementary languages such as PSL and assesses key verification
technologies such as functional coverage and formal verification.
Duration
4 days. We can also offer standard or customized versions of this workshop onsite
or at the location of your choice.
Objectives
- To make the most of VHDL’s capabilities for testbench design
- To explain key verification techniques and technologies and to
understand how these complement and integrate into a VHDL verification flow.
- To introduce the Property Specification Language (PSL), which
builds on VHDL syntax to enable Assertion Based Verification (ABV); functional coverage
and formal verification.
- To understand the techniques you can use today, on your current project,
to increase your verification efficiency.
Prerequisites
Delegates should be familiar with writing and simulating VHDL, e.g.
from attendance at an Esperan VHDL Application Workshop.
Some project design and verification experience is useful, but not essential.
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VERIFICATION WITH VHDL |
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