Esperan - Verification with VHDL Training : Agenda


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Verification with VHDL : Technical Details

Overview & booking

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Course Summary

Testbench Design with VHDL
Specialized language constructs, coding techniques and methodologies for making the most of VHDL for effective testbenches and design verification.
Verification Techniques and Methodologies
Explaining techniques such as TLM, ABV and randomization, demonstrated with VHDL code, and introducing powerful verification languages such as PSL and SystemC.
Verification Technologies Overview
Pragmatic descriptions, coupled with impartial assessments, of current verification technologies, many of which are available in commercial VHDL simulators or enabled by extension languages such as PSL.

Workshop Agenda

Verification Overview
Creating a simple test plan
Creating a simple testbench

Simple stimulus
Test data arrays
File IO

Adding self test

Assertion construction
Timing assertions
Hierarchical references

Assertion Based Verification (ABV)

VHDL limitations
OVL assertion checks
Property Specification Language (PSL)

Introduction to PSL

Foundation language
SERE’s
AMBA protocol example

Testbench abstraction

Procedures and parameters
Stimulus procedures
Side-effects

Robust procedures

Bus protocol procedures
Interrupts, timeouts, traps, early response and channels
Writing reusable procedures

Transaction Level Modelling (TLM)

What is TLM?
Transactor structures
TLM testbench architectures

File operations

EOL, EOF, comments
Script driven testbench
Dynamic file IO
Binary file IO

Code Analysis

Linting/code purifiers
Static coverage metrics
Functional coverage

Random stimulus

Pseudo-random number generators
Distribution control
Weights and constraints

Random methodology

Testbench structure
Random test-sets
Directed corner cases
HVL randomization

Beyond HDL

High-level Verification Languages (HVL)
C/C++ testbenches
SystemC and IEEE1647

C Testbench

C verification models
Foreign Language Interface (FLI)
Writing FLI models
SystemC alternatives

Static Verification Methods

Static Timing Analysis
Equivalence Checking
Property Checking

Putting it all together

Verification methodology

Conclusions and Next Steps

Appendices:

Simulation efficiency coding guidelines
Dynamic data structures
Emulation

Workshop Labs
The workshop labs aim to give you practical experience of testbench writing and verification tools and technologies. Some labs are tool-specific, e.g. PSL and C testbenches. Contact Esperan for details of supported tools.

The lab sessions include

Familiarization with simulation and synthesis tools
Self-checking array-based testbenches
Simple PSL assertions
AMBA bus Transaction Level Modeling
Advanced ASCII and binary files
C testbenches
Random stimulus generation
Dynamic data types

Overview & booking

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		Esperan has been providing VHDL training and Verilog training in UK, US, Canada, Western Europe, South Africa and throughout the world.

Esperan contact information	US contact information
Phone +44 1344 865436 Fax +44 1344 865347 Email info@esperan.com	Tollfree Tel. 1800 220 8148 Fax. 1888 641 6431 Email US-sales@esperan.com