Rational

No prior knowledge of C++ or HDL is required for the completion of this tutorial; however, throughout this tutorial we will be drawing parallels between SystemC and other languages.

Note this is a deliberately simplified description of SystemC. Full details on the language, coding styles; design guidelines can be found on the Esperan SystemC Fundamentals class.

Introduction

Why SystemC instead of C++

SystemC Implementation

Modules

class counter: public sc_module {
  int value;
public:
  sc_in clk;
  sc_in count;
  sc_in reset;
  sc_out q;

  SC_HAS_PROCESS(counter);

  counter(sc_module_name nm): sc_module(nm), value(0) {
  SC_METHOD(do_count);
    sensitive<< clk.pos() << reset ;
  }
protected:
  void do_count() {
    if (reset) { value = 0; }
    else if (count) { 
      value++;
      q.write(value);
    }
  }
};

The constructor function is used to register any of the access functions as concurrent processes. In this case, the do_count function is registered an SC_METHOD which is similar to a Verilog always or a VHDL process. It is worth observing that the constructor function defines a parameter of type sc_module_name. This parameter is required by the sc_module parent class. For the sake of simplicity, this parameter can be seen as a string type.

The last part of this module defines the do_count function. At this point, it can be observed that the do_count function is being made sensitive to the reset port and the positive edge of the clk port. Consequently, it will only be activated on a change of either the reset or the clk ports.

Ports and Interfaces

Although SystemC provides numerous predefined ports such as: sc_in<>, sc_out<>, sc_inout<>, sc_fifo_in<>, sc_fifo_out<>, and more, the language also allows the definition of user defined ports and how should they be accessed. This is done through the use of the sc_port<> class. An example of the use of the sc_port is as follows:

sc_port< sc_signal_in_if, 1 > clk;

sc_in clk ;

The interface sc_signal_in_if<> defines the restricted set of available messages that can be send to the port clk. For instance the functions: read() or default_event() are defined by the sc_signal_in_if<> class. At this stage it worth pointing out that the implementation of the functions defined inside an interface is provided by a third party element: the channel. Channels will be discussed in greater detail at the end of this section.

Processes

By definition, SC_METHOD cannot be suspended during its execution. Once the execution of the SC_METHOD as been performed, it halts and waits for new activities on its static or dynamic sensitivity list before executing again. This is similar to a VHDL process or Verilog procedure with a sensitivity list.

In contrast with SC_METHOD, SC_THREAD can be suspended during execution and resumed at a later stage. Furthermore, by definition, SC_THREAD only executes once during simulation and then suspends. This mechanism is akin to a Verilog initial block. For this reason, designers will commonly use an infinite loop inside an SC_THREAD to prevent it from ever exiting before the end of the simulation. An example of an SC_THREAD is as follows:

void do_count() {
  while(true) {
    if (reset) { value = 0; }
    else if (count) { 
      value++; 
      q.write(value); }
    wait(); 
  }
}

Channels

Note: For the purpose of this tutorial we will only consider predefined SystemC channels.

Composition

class testbench: public sc_module {
public:
  sc_out clk;
  sc_out reset;
  sc_out count;
  SC_HAS_PROCESS(testbench);

  testbench(sc_module_name nm): sc_module(nm) {
    SC_THREAD(clk_gen);
    SC_THREAD(stimuli);
  }

  void clk_gen() {
    while(true) {
      clk.write(true);
      wait(10, SC_NS);
      clk.write(false);
      wait(10, SC_NS);
    }
  }

  void stimuli() {
    while(true) {
      reset.write(true);
      count.write(false);
      wait(10, SC_NS);
      reset.write(false);
      wait(50, SC_NS);
      count.write(true);
      wait(200, SC_NS);
    }
  }
};

The next step consists of instantiating a counter and a testbench object inside a top level module as follows:-

class top: public sc_module { 
public:
  sc_signal clk_sig, count_sig, reset_sig;
  sc_signal q_sig;

  counter uut ;   // Counter instance
  testbench tb ;  // Testbench instance

  top(sc_module_name nm): 
    sc_module(nm), uut("uut"), tb("tb") {
    // Testbench’s ports connection
    tb.clk(clk_sig);
    tb.reset(reset_sig);
    tb.count(count_sig);

    // Counter’s ports connection
    uut.clk(clk_sig);
    uut.reset(reset_sig);
    uut.count(count_sig);
    uut.q(q_sig);
  }
};

instance_name.port_name(channel_name);

Simulation

This function will execute simulation specific commands such as setting the simulator’s resolution, channels to be traced, top level instance, simulation running time and more. An example of a sc_main function is as follows:-

int sc_main(int argc, char* argv[])
{
  sc_set_time_resolution(1, SC_NS);
  top verif_env("verif_env");  // Top level instance

  // Creating a trace file
  sc_trace_file *tf;
  tf = sc_create_vcd_trace_file("trace");
  sc_trace(tf, verif_env.clk_sig, "clk_sig");
  sc_trace(tf, verif_env.reset_sig, "reset_sig");
  sc_trace(tf, verif_env.count_sig, "count_sig");
  sc_trace(tf, verif_env.q_sig, "q_sig");
 
  // Running the simulation
  sc_start(1000, SC_NS);
  sc_close_vcd_trace_file(tf);
  return (0);
}

Conclusions

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