What is SystemVerilog?
SystemVerilog is a substantial upgrade of Verilog2001, with the aim of
defining a concise, unified language for both design and verification using a single
simulation tool. It is an IEEE standard IEEE-1800-2005.
SystemVerilog adds a considerable amount of new content. The IEEE-1800 Language Reference Manual contains:-
- Over 90 new keywords
- 30 different sections
- Over 600 pages of all new content
The new features added by SystemVerilog can be roughly broken into 2 groups.
Design features improve the productivity, readability, and reusability of RTL code. Features in this
category are intended to be synthesizable and used by designers for block-level design.
Verification features add the necessary language constructs to enable modern verification techniques such
as constrainted randomization; Assertion-based Verification(ABV); object-oriented design and functional coverage.
Design Features Summary
- Data Types
- Relaxation of rules on existing data types
- New pre-defined data types
- User-defined data types and objects
- New declaration regions for types
- Convenience and Synthesis Features
- New operators
- Connectivity simplification
- New and improved procedural statements
- Replacements for full_case and parallel_case synthesis directives
- Specialised always procedures for combinational, registered and latched logic
- Enhancements to subprograms
- Interfaces to encapsulate communication between modules
Verification Features Summary
- Data Abstraction
- 2-state, enumerated, structured and user-defined types
- Improved control of processes
- Final blocks, fork/join extensions, events, fine-grained process control
- Race-free stimulus generation with program blocks
- Easier definition of timing with clocking blocks
- Dynamic data structures
- Dynamic arrays, associative arrays and queues
- Object-Oriented design
- Class-based objects similar to SystemC and C/C++ capabilities
- Interfaces for Transaction-Level Modeling (TLM)
- Direct Programming Interface (DPI)
- Simple, lightweight interface for C code
- Features enabling advanced verification techniques
- SystemVerilog Assertions (SVA) for Assertion-based Verification (ABV)
- Covergroups and cover assertions for functional coverage
- Randomization constructs for both simple and class-based data with constraints and weighting
Back to top
