| Free parsing and folding text editor with VHDL mode and Control Structure Diagram
(CSD) intended to improve readability of source code. |
| The Regex Coach is a great interactive application to help learn,
create and debug Regular Expressions (Regex), used in many languages such as
Perl and Tcl as well as being a
key component of many UNIX utilities.
|
| Small application for creating Linear Feedback Shift Registers (LFSR's) up to 16 bits
in length with automatic generation of HDL code. Xilinx have a great
application note XAPP052 (PDF)
describing the background and application of these very useful circuits.
|
| GHDL - Free VHDL Linux Simulator |
| Free, open-source VHDL simulator for Linux released under the GNU license.
|
| Fully-featured, low cost VHDL tool suite, including simulator, Graphical User Interface, waveform viewer,
project manager and language-sensitive editor. Now with a free license for the restricted version until March 2006. |
| Download a free Student version of the Blue Pacific BlueHDL simulator for
VHDL, Verilog and SystemC. Unfortunately this software is now only available for Windows95, 98 and NT.
|
| Project to create a free VHDL simulator for Linux under the GPL license. |
| Superb documentation system for C++, C, SystemC and other object-oriented languages. Creates an online,
fully linked graphical represention of any source code automatically, making it a great tool
for extracting the code structure of unknown or undocumented code.
See it in
action with the SystemC2.1 release.
|
| VHDLDOC is a tool to generate automatically hyperlinked html-documentation of VHDL code.
Not quite as sophisticated as the Verilog HTML convertor below, and with some strict coding conventions,
but useful for exploring undocumented or unfamiliar code. |
| Cool Verilog documentation tool which turns Verilog code into HTML pages. Includes linked
hierarchial references, color syntax highlighting, signal/object tracing and index of design objects. |
