 |
Course Menu |
 |
|
|
|
 |
VHDL Training |
|
| |
|
|
|
|
|
| |
Verilog Training |
|
| |
|
|
|
|
|
| |
SystemVerilog |
|
| |
|
|
|
|
|
| |
PSL Training |
|
| |
|
|
|
|
|
| |
Specman Elite & e |
|
| |
|
|
|
|
|
| |
C++/SystemC |
|
| |
|
|
|
|
|
| |
PCB Design |
|
| |
|
|
|
|
|
| |
Tcl/Tk and Perl |
|
| |
|
|
|
|
|
| |
FPGA Design |
|
| |
|
|
 |
|
|
|
|
|
TCL Scripting for EDA Workshop: Technical Details
Course Summary
Language Basics
Language concepts and constructs, including understanding how a Tcl script is
interpreted; use of quotes "", braces {} and brackets []; Tcl operators and functions;
creating procedures, and script control flow commands.
Manipulating Data
Examining the distinctions between strings, lists and arrays; building and manipulating
data structures and exploiting regular expressions to search, extract and edit source
data.
Interacting with the External Environment
File access; channel buffering; Tcl processes; accessing external programs; turning
scripts into applications; use of libraries and packages.
EDA Applications
Both generic and EDA tool-specific applications are included in the course, e.g.
searching and editing report files and source code; monitoring signal simulation activity;
multi-pass synthesis with analysis.
Course Features
Here are the specific aspects of the workshop which distinguish it from Tcl text
books and other Tcl workshops:-
- EDA-specific content
- EDA case studies of using Tcl in real-world situations.
- Sample EDA Tcl scripts provided with the course material.
- Summaries of Tcl use in market-dominant EDA tools.
- No need to study thick books - start solving real problems with Tcl straight away.
- Designed by EDA engineers for EDA engineers
- Considers Tcl script performance and optimization.
- Examples extracted from real-world scripts.
- Considers portability between UNIX and Windows platforms.
- Many useful pointers and coding recommendations applied throughout the course.
- Compact course, but covers wide variety of topics including practical examples of:-
- EDA netlist hacking.
- Simple client-server networking.
- Interprocess-communication to allow interaction between otherwise incompatible tools.
- Driving interactive programs for design file backup or server batch processing.
- Entertaining teaching approach in a relaxed classroom atmosphere
- The material uses lots of graphics to help visualize difficult concepts throughout the course
Workshop Agenda
- Introduction
- Tcl basics
- Commands
- Grouping with "" and {}
- Variables
- Variable, backslash and command substitution
- Command evaluation
- Operators
- Arithmetic operators
- Mathematical functions
- Numerical accuracy
- Basic procedures
- Basic file manipulation
- Lab: Data type conversion
- Control flow
- Conditional constructs
- Loop commands
- Syntax summary: braces and spaces
- Strings
- String construction
- String commands
- Glob-style match patterns
- Formatting and scanning
- Indexing strings
- Binary strings
- Lab: Extracting design data
- Lists and arrays
- Building lists
- Manipulating elements
- Lists versus strings
- Searching and sorting
- Basic array operations
- Multi-dimensional arrays
- Lists versus arrays
- File manipulation
- File basics
- Opening and closing files
- Reading lines and characters
- Binary file access
- Channel buffering
- Invoking external programs
- Processes in Tcl
- Safe interpreters
- Networking
- Regular expressions
- Basics
- Extracting information from source code
- Filtering command logs
- Editing using string substitution
- Lab: VHDL netlist hacking
- Scripts and applications
- Command line arguments
- Dealing with platform-specific issues
- Procedures reviewed
- Variant arguments
- Variable scope
- Catching and handling errors
- Tcl packages
- Tcl in EDA tools
- Expect: interacting with command line programs
Workshop Labs
As well as short lab exercises illustrating the
use of specific language features, the course
includes several generic and EDA tool-specific
labs.
The labs sessions include:-
- Simple simulation and synthesis scripts
- Report file parsing
- Testbench builder
- Signal activity monitor
- Multi-pass synthesis with results analysis
To Top
|
|
|
 |
|
News |
| |
|
|
|
|
| |
|
Technical Assets |
|
|
| |
Tutorials |
| |
|
|
|
|
| |
Hardware |
| |
|
|
|
|
| |
Software |
| |
|
|
|
|
| |
Webseminars |
| |
|
|
|
|
|
| |
|
Course
Schedule |
|
|
|
| |
|
|
|
|
| |
|
For over 10 years.. |
|
|
|
| |
Esperan has been providing VHDL training
and Verilog training in UK, US, Canada, Western Europe, South Africa and throughout the world. |
|
|
|
