SystemVerilog Design Module
Describing the considerable enhancements for RTL design. Topics include new data types,
constructs and operators; ease-of-use improvements for procedures and subprograms;
solutions for existing synthesis issues; new user-defined data types and structures;
and major reforms for hierarchical connectivity such as automatic port connections,
packages and interfaces.
SystemVerilog Verification Module
Exploring the major new features in SystemVerilog for writing testbenches and verifying
designs. Topics include clocking and program code blocks for testbench functionality
and timing; Object-Oriented design features; functional coverage; generation of
random stimuli; verification data structures; assertions and integrating C code
into SystemVerilog testbenches.
This module also examines how these new features enable powerful verification
techniques such as Transaction Level Modelling (TLM); Assertion-Based Verification (ABV);
functional coverage and randomization of test data.
Verification of a simple CPU using SystemVerilog verification constructs.
Using SystemVerilog features to explore Transaction Level Modelling (TLM); randomization; functional coverage and Assertion Based Verification (ABV) techniques.
