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SystemVerilog for Design and Verification : Overview & Booking
What is SystemVerilog?
SystemVerilog is a major extension to Verilog2001, adding significant new features to Verilog
for verification, design and synthesis. Enhancements range from simple new language constructs
to the addition of Object-Oriented design features. There are also considerable improvements
in the usability of Verilog for RTL design. A summary of SystemVerilog design features can be
found in our free tutorial download.
Overview
Esperan’s SystemVerilog course gives you an in-depth introduction to the main enhancements
that SystemVerilog offers, discussing the benefits and issues with the new features and
demonstrating how design and verification is more efficient and effective when using
SystemVerilog constructs. The course breaks down into two modules. The Design module
examines improvements for RTL design and synthesis; and the Verification module explores
verification enhancements such as object-oriented design, assertions and randomization.
Duration
5 days, consisting of a 2 day Design module and a
3 day Verification module. . We can also offer standard or customized versions of this workshop onsite or at the location of your choice.
Objectives
- To explore the new features of SystemVerilog for design and verification
and demonstrate the improvements in design efficiency from their use.
- To examine the full range of SystemVerilog improvements for RTL design,
including new data types and statements; changes to Verilog language rules;
fixes for case synthesis issues and powerful new connectivity features.
- To explain key features for verification, such as classes, randomization and
assertions, and illustrate how to exploit these features for more efficient
verification and testbench design.
Prerequisites
Delegates must be familiar with Verilog and ideally, but not essentially, Verilog2001. No prior knowledge of SystemVerilog is required.
If you have queries on these prerequisites, please contact Esperan (info@esperan.com)
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SYSTEMVERILOG FOR DESIGN AND VERIFICATION |
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