|
SystemVerilog Assertions (SVA) : Technical Details
Now available with an optional third day on Advanced SVA and Formal Verification
Course Structure
The workshop is based around a 2-day agenda. We can also offer standard or customized versions of this workshop onsite or at the location of your choice.
Course Summary
SystemVerilog Assertion (SVA) Fundamentals
Explaining the benefits and issues with Assertion-Based Verification (ABV).
Understanding immediate and concurrent assertions.
Describing how simple boolean expressions can be built up into powerful, conditional assertions.
Sequences
Exploring SVA sequences, which allow the definition of multi-cycle design properties.
Analyzing sequence design properties to understand their strength and weaknesses.
Using replication and composition operators to describe complex parallel, alternate
and overlapping design protocols.
Coding Guidelines and Methodologies
Demonstrating good and bad coding styles; using parameters and nesting to create compact,
reusable assertions and defining a methodology for writing sophisticated transaction-based
assertions.
Workshop Agenda
- Assertion Based Verification (ABV)
- Immediate and Concurrent Assertions
- Procedural assertions
- Limitations of immediate assertions
- Concurrent assertion
- Terminology
- Assertion Basics
- Assertion structure
- How to build simple assertions
- Clocked and unclocked properties
- Default clocks
- Assertion placement
- Conditional assertions (implication)
- Overlapping evaluation
- Using built-in functions
- Sequences
- Sequence introduction
- Sequential implication
- Sequential property analysis
- Disabling Properties
- Cycle repetition
- Sequence repetition
- Analysis of repetition examples
- Sequence Composition
- Named sequences
- Sequence clocking
- Overlapping and alternate sequences
- Parallel sequences
- throughout and within
- Advanced SVA Features
- Evaluation of properties and assertions
- Detecting the end of a sequence
- Parameterized sequences and properties
- Actions for passed or failed properties
- Assertion variables
- Using Expect
- External assertions and binding
- Coding Guidelines and Avoiding Common Problems
- Abstraction levels
- Over and under constrained assertions
- Overlapping
- Never failing constructs
- Assertion refinement with arbiter case study
- Coverage
- What is coverage?
- Structural and functional coverage
- Coverage of the arbiter design
- Coverage applications
- Practical SVA Application
- Transaction-Based assertion modelling and refinement using an AMBA bus protocol
- Introduction to Static Formal Verification
- Static and dynamic verification
- Model checking
- Properties and constraints
- Conclusions and Next Steps
- Appendices
- Index
Workshop Labs
The workshop labs aim to give you practial experience of assertion
writing; practice in managing and debugging SVA assertions in simulation and an
understanding of the methodology of applying assertions to realistic designs.
Lab exercises include:-
- Familiarization with managing and debugging SVA assertions in a simulation environment
- Exploration of SVA features using increasingly complex designs, including an FSM, FIFO and arbiter
Overview & booking
|
