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SystemC Transaction Level Modeling (TLM) : Technical Details
Course Structure
The course comprises 3 main sections. The Interfaces and Channels section covers a detailed study
of the available building components for TLM descriptions whereas the Programmer´s View and
Programmer´s View Timed section explore design methods and practical examples of
TLM modeling.
Interfaces and Channels
Describing the existing TLM interfaces and associated channels. Topics include,
definitions of blocking, non blocking, bidirectional and unidirectional
interfaces; implementation of TLM channels such as queues; and TLM layering principles.
Programmer´s View (PV)
Examining the steps involved in crafting protocol layers and versatile data structures.
Looking at practical examples of using Instruction Set Simulators (ISS) in the
Programmer´s View abstraction level. Applying design techniques to improve
simulation performances. PV models case studies.
Programmer´s View Timed (PVT)
Covers the requirements for PVT models. Illustrates the implementation of a PVT model
by looking at a practical timed design example as well as inter-module arbitration policies.
Workshop Agenda
- Introduction to Transaction Level Modeling
- What is TLM
- Motivations for a TLM standard
- Terminology
- RTL versus TL modeling
- TLM design methodology
- SystemC 2.1 refresher
- The SystemC program structure
- Threads and methods
- Interfaces
- Predefined and user defined ports
- Hierarchical channels
- sc_export principles
- TLM Predefined Interfaces
- SystemC model of computation
- SystemC based TLM modeling
- TLM interface implementation
- Blocking vs non-blocking interfaces
- Bidirectional vs unidirectional interfaces
- TLM Channels and Communication Layers
- Master/slave terminology
- TLM channel principles
- tlm_fifo channel
- tlm_req_rsp_channel channel
- TLM layering
- Programmer's View
- The protocol layer
- Data structures
- SystemC implementation
- Introducing an ISS inside the programmer's view
- Performances considerations in the PV
- PV Design worked example
- Timed TLM modeling (PVT)
- Understanding the notion of time in TLM models
- Implementations of a basic protocol environment
- Delays modeling alternatives
- Arbitration Policies
- What are the needs for arbitration
- Where to locate arbitration
- Implementation of arbitration schemes
Workshop Labs
- Lab1: Rapid platform assembly
- Lab2: Platform debug and analysis
- Lab3: Slave module creation
- Lab4: Modules basic synchronization
- Lab5: Slave access with timing
- Lab6: Channel access with timing
- Lab7: Creation of a memory controller
- Lab8: Use of an arbitrated basic channel
Overview & booking
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