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Technical Summary
Essential C++ for SystemC
Overview of essential C++ required to fully utilize SystemC, including object-oriented concepts,
constructs, organization, pitfalls, and standard libraries.
SystemC Language Basics
The central concepts of SystemC, together with an overview
of fundamental building blocks, language constructs and design
and simulation environment.
Ports, Interfaces and Channels
Detailed background on the use and application of these powerful
communication constructs for verification using Transaction
Level Modelling.
Verification and Simulation Debug
Exploration of the SystemC features for controlling simulation,
navigating and annotating the design hierarchy and reporting
on simulation activity.
Workshop Agenda
Essential C++ for SystemC
- Writing a simple program
- Intrinsic Data Types
- Operators & Expressions
- Control Flow Statements
- Functions
- Program Stucture
- Arrays & Pointers
- Object Storage
- Class & struct
- Constructors & Destructors
- Object Modelling
- Operator Overloading
- Single Inheritance
- Polymorphism & Dynamic Binding
- Multiple Inheritance
- I/O Stream Class Library
- Templates
Fundamentals of SystemC
- SystemC Introduction
- Scope and architecture
- Design and simulation environment
- Language Introduction
- Modules
- Constructor & destructor
- Ports and port templates
- Channels & processes
- Creating hierarchy
- Makefiles
- Data Types
- Time
- Bit and integer types
- Vectors
- Strings and Characters
- User-defined types
- Fixed point data
- Interfaces and Channels
- Ports and templates
- User defined ports
- Port and interfaces
- Interface methods
- Registering ports
- Channel definitions
- Primitive channels
- User-defined channels
- Channel hierarchy
- Design example
- Processes and events
- Processes reminder
- Registration
- Static sensitivity
- Dynamic sensitivity
- Simulation
- Time unit and resolution
- Scheduling
- Queues
- Event notification
- Simulation query and control
- Clock generation
- Exploring a design structure
- User defined attributes
- Setting and retrieving attributes
- Traversing the design hierarchy
- Debugging in SystemC
- Trace files
- Customizing traces
- User-defined types
- SystemC assertions
- SCV Overview
- SystemC Verification library
- CVE extensions
Appendices
- C++ Reference
- NC-SystemC Design Flows
Workshop Labs
The lab exercises begin with simple C++ examples to build C++ experience, and continue with a small, simple but complete telecoms networking example to illustrate a SystemC design methodology as well as teaching language syntax.
- C++ Development Environment
- Basic C++ programming
- Object Oriented example
- Operator overloading
- Familiarization with SystemC tools and environment
- Structured design of a network transmission module with CPU interface
- Implementation of a network protocol using channels
- System verification using a channel and transactor
- Exploiting SystemC abstraction features
- Mixed HDL SystemC and HDL design (optional)
Overview & booking
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For over 10 years.. |
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Esperan has been providing VHDL training
and Verilog training in UK, US, Canada, Western Europe, South Africa and throughout the world. |
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