What is SVA?
SystemVerilog Assertions (SVA) are part of the SystemVerilog language. SVA is an industry and IEEE (IEEE1800) standard language for specifying design properties (assertions), functional coverage and constraints. SVA can be embedded in HDL code and used in both simulation and Formal Verification, enabling a sophisticated and complete Assertion Based Verification (ABV) methodology.
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Overview
This Advanced SVA and Formal Verification course builds upon Esperan´s 2 day SystemVerilog Assertions course to demonstrate advanced SVA features and introduce a methodology for using SVA in both Formal Verification and simulation. This course may be taken stand-alone for delegates with existing SVA knowledge, or as an add-on to the SystemVerilog Assertions course.

Duration 1 day.

Objectives

• To demonstrate how to bind SVA modules to existing designs of any language.
• To introduce the concepts, terminology, benefits and limitations of Formal Verification.
• To describe a methodology using SVA in both simulation and Formal verification.
• To provide practical experience of using SVA in Formal Verification and hybrid verification.

Prerequisites
Delegates should have attended the Esperan 2 day SystemVerilog Assertions course or have advanced working knowledge of HDL's, SVA and simulation techniques. If you have queries on these prerequisites, please contact Esperan (info@esperan.com).