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FPGA Design |
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Designing with Altera® Stratix® FPGAs: Technical
Details
Course
OverView
Course Summary
Stratix FPGA Technology
in Depth
Detailed description of the device architecture, including
logic structure; memory; clock networks and interconnect,
IO, and interface features.
Exploiting New Stratix
FPGA Design Features
Effective use of TriMatrixTM memory architectures; dedicated
DSP blocks; MultiTrackTM interconnect and clock management.
Using Stratix FPGAs in
an HDL Design Flow
Using MegaFunction cores; modular design using LogicLockTM design flow;
multi-clock timing analysis; achieving timing convergence;
gate level simulation and device configuration.
Course Agenda
Day 1:
- Stratix FPGA Overview
- Stratix FPGA architecture
- Logic Element (LE)
- Logic Array Block (LAB)
- TriMatrix
memory
- DSP blocks
- Phase Locked Loop (PLL) features
- Interconnect, IO and memory interfaces
- Logic Structure
- LE I/O’s, modes and register controls
- Reset and initialisation
- LAB structure
- TriMatrix
memory
- Organization, modes and features
- M512, M4K, MegaRAM memory blocks
- Altera MegaWizard® plug-in manager
- MegaFunction modules
- MegaFunctions in an HDL design flow
Day 2:
- Interconnect and routing
- Clock and global nets
- DirectDriveTM technology
- Local, DirectLink and MultiTrack interconnect
- Clock management and Phase Locked Loops
(PLL)
- Enhanced and Fast PLL
- New PLL features and operation modes
- LogicLock design flow
- LogicLock design flow goals and applications
- LogicLock design flow in a hierarchical design flow
- I/O Features in Stratix FPGAs
- I/O architecture and routing
- Double Data Rate (DDR)
- Memory interfaces
- High Speed Differential I/O (HSDI)
- HSDI resources
- HSDI and Fast PLL
Day 3:
- Stratix FPGA DSP Blocks
- DSP block architecture
- Pipelined multiply-accumulate operations
- Operation modes
- FIR and IIR filtering
- Timing analysis in Quartus® II design software
- Single clock system analysis
- Timing assignments
- Multi-clock domain systems
- Multi-cycle path assignments
- Gate level simulation
- VITAL libraries
- SDF annotation
- Simulation issues
- Device configuration
- Configuration devices
- Programming Stratix FPGAs
- Enhanced Configuration
- Remote & local update
- PowerGaugeTM power estimation
Workshop Labs
The lab exercises demonstrate how the design
flow is used in real life design situations. Delegates will
experience the entire design flow in detail, through RTL simulation;
synthesis; Place and Route; timing analysis and gate level
simulation. The labs concentrate on how to use the tools effectively
rather than writing source code.
The lab sessions include
- Use of PLL, LVDS, FIFO and Double Data
Rate I/O MegaWizard plug-in manager components
- Advanced multi-clock domain timing analysis
- Improving Fmax and device utilization
- Applying effective synthesis constraints
- Tracing and fixing timing violations
- Understanding how to use Altera simulation
libraries
- Clock domain synchronization
- Using the LogicLock design flow
Altera, Stratix, MegaWizard, Quartus, MultiTrack, TriMatrix,
LogicLock, DirectDrive, and PowerGauge are the trademarks of Altera Corporation
in the U.S. and other countries.
Course
OverView
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For over 10 years.. |
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Esperan has been providing VHDL training
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