 |
Course Menu |
 |
|
|
|
 |
VHDL Training |
|
| |
|
|
|
|
|
| |
Verilog Training |
|
| |
|
|
|
|
|
| |
SystemVerilog |
|
| |
|
|
|
|
|
| |
PSL Training |
|
| |
|
|
|
|
|
| |
Specman Elite & e |
|
| |
|
|
|
|
|
| |
C++/SystemC |
|
| |
|
|
|
|
|
| |
PCB Design |
|
| |
|
|
|
|
|
| |
Tcl/Tk and Perl |
|
| |
|
|
|
|
|
| |
FPGA Design |
|
| |
|
|
 |
|
|
|
|
|
NEW! Advanced SpecMan Elite : Agenda
Course Agenda
Day 1
- ICPM overview
- Overview of entire verification process
- How different verification technologies fit together
- Getting the most out of verification environment reuse
- Importance of verification planning
- Reference Models
- Purpose of reference models
- Interface t
- other languages, SystemVerilog/SystemC, C++, C
- Implementation of reference models
- Advanced Coverage Implementation
- Reference Model vs. DUT coverage
- Abstracting coverage t
- reference model
- Different kinds of per instance coverage
- When to sample
- Coverage reusability
Day 2
- Module to System reuse
- Introduction to System Verification
- Introduction to System eVCs
- Packaging
- Module and System eVC Architecture
- Integrating eVCs
- eVC Configuration
- Sequences
- SystemCoverage and Checking
- Intelligen
- Technical Concepts of new random generator
- New Generator Debugger
- Using the generator Linter
- Migration of Existing Environments
- Procedural Coding Guidelines
- Backward Compatibility Issues
- Macros
- Extending the e language with macros
- Computed macros
- Macr
- development
- Debugging Macros
Day 3
- Efficient use models for Specman
- Compiled and interpreted e code
- Profiler
- irun utility
- Optimizing Regression Performance
- Advanced Temporal Expressions
- Advanced temporal operators
- Methodology recommendations
- One shot checks
- Event coverage
- Advanced Message Loggers
- Basic Logger Operations
- How Loggers can be Configured
- How Specman deals with messages
- Using Colour
- Advanced Logger Implementation Issues
Day 4
- Debugging
- Packing/Unpacking
- Objections
- Runtime errors
- Simvision interface
- Tips and tricks
- Advanced Sequences
- Interrupt Sequences and grabbing
- Virtual Sequences
- Layered Sequences
- Generation aspects of Sequences
- Register and Memory Modeling
- Using the vr_ad package
- Backdoor access
- Visualisation tools
|
|
|
 |
|
News |
| |
|
|
|
|
| |
|
Technical Assets |
|
|
| |
Tutorials |
| |
|
|
|
|
| |
Hardware |
| |
|
|
|
|
| |
Software |
| |
|
|
|
|
| |
Webseminars |
| |
|
|
|
|
|
| |
|
Course
Schedule |
|
|
|
| |
|
|
|
|
| |
|
For over 10 years.. |
|
|
|
| |
Esperan has been providing VHDL training
and Verilog training in UK, US, Canada, Western Europe, South Africa and throughout the world. |
|
|
|
