SystemC Verification (SCV): Overview & Booking

What is SCV?
SystemC is increasing being adopted for the verification of VHDL and Verilog designs and systems. However SystemC lacks some essential features for applying proven verification techniques such as randomization, Transaction Level Modeling (TLM) and dynamic resource allocation. The SystemC Verification (SCV) library is a free extension library to SystemC which enable these advanced verification techniques to be used in SystemC testbenches for HDL designs.

Overview
Esperan´s SCV course describes the background to advanced verification techniques such as Transaction Level Modeling, randomization and dynamic resource generation. The course details the features of the SCV library and demonstrates how SCV features can be used to implement these verification techniques in SystemC testbenches.
The huge productivity gains in verification which can be seen in adopting SCV make this course an absolute must for all SystemC users.

Duration
2 days. We can also offer standard or customized versions of this workshop onsite or at the location of your choice.

Objectives

• To explain and illustrate the advantages of SCV extensions for verification; testbench design and advanced data manipulation.
• To explore the benefits of randomization techniques for verification.
• To give you a thorough background in the principles of Transaction Level Modelling (TLM) and the supporting features in SCV.
• To give you hands-on practical experience in applying SCV.

Prerequisites
Delegates must have a good working knowledge of SystemC, e.g. by attendance on the Esperan SystemC Workshop. No prior knowledge of SCV is assumed. If you have any queries on the prerequisites for these courses, please do not hesitate to contact Esperan.