Esperan - European Course Schedule


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	SystemVerilog Design SystemVerilog Verification SystemVerilog Assertions SVA & Formal Verification

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	Verification with PSL PSL & Formal Verification

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	e Verification Environments Advanced Verification

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	Verification with C++ SystemC Fundamentals Verification with SystemC Transaction Level Modeling

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	High Speed PCB Design Minimising EMI

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Public Course Schedule for France, Germany and Italy 2008

Velizy France

For further information or to register, please contact Esperan France.

25-Jun-2008	SystemC Fundamentals	5 Days
1-Jul-2008	Designing with VHDL	4 Days
7-Jul-2008	SpecMan Elite Verification Environment	5 Days
8-Sep-2008	SystemVerilog for Design and Verification	5 Days
22-Sep-2008	Verification with PSL	2 Days
29-Sep-2008	SpecMan Elite Verification Environment	5 Days
6-Oct-2008	Designing with VHDL	4 Days
13-Oct-2008	Verilog Application Workshop	5 Days
20-Oct-2008	VHDL Application Workshop	5 Days
5-Nov-2008	Verification with PSL	2 Days
17-Nov-2008	SpecMan Elite Verification Environment	5 Days
24-Nov-2008	SystemVerilog for Design and Verification	5 Days
1-Dec-2008	Verification with VHDL	4 Days
8-Dec-2008	High-speed PCB Design	3 Days
8-Dec-2008	Verilog Application Workshop	5 Days
11-Dec-2008	Minimising EMI	2 Days
15-Dec-2008	VHDL Application Workshop	5 Days

Munich Germany

For further information or to register, please contact Esperan Germany.

19-Jun-2008	TCL Scripting for EDA	2 Days
23-Jun-2008	Verilog Application Workshop	5 Days
26-Jun-2008	Perl Programming	2 Days
7-Jul-2008	SpecMan Elite Verification Environment	5 Days
10-Jul-2008	Perl Programming	2 Days
28-Jul-2008	VHDL Application Workshop	5 Days
31-Jul-2008	TCL Scripting for EDA	2 Days
4-Aug-2008	Verilog Application Workshop	5 Days
11-Aug-2008	Verification with PSL	2 Days
18-Aug-2008	SystemVerilog for Design and Verification	5 Days
21-Aug-2008	Perl Programming	2 Days
25-Aug-2008	SystemVerilog Assertions	2 Days
26-Aug-2008	Specman Elite Advanced Verification	3 Days
1-Sep-2008	High-speed PCB Design	3 Days
4-Sep-2008	Minimising EMI	2 Days
15-Sep-2008	SpecMan Elite Verification Environment	5 Days
29-Sep-2008	Verification with PSL	2 Days
6-Oct-2008	SystemVerilog for Design and Verification	5 Days
8-Oct-2008	SystemC Fundamentals	5 Days
16-Oct-2008	Perl Programming	2 Days
20-Oct-2008	Verilog Application Workshop	5 Days
27-Oct-2008	SpecMan Elite Verification Environment	5 Days
3-Nov-2008	SystemVerilog Assertions	2 Days
6-Nov-2008	TCL Scripting for EDA	2 Days
10-Nov-2008	VHDL Application Workshop	5 Days
18-Nov-2008	Specman Elite Advanced Verification	3 Days
24-Nov-2008	High-speed PCB Design	3 Days
27-Nov-2008	Minimising EMI	2 Days
1-Dec-2008	SystemVerilog for Design and Verification	5 Days
15-Dec-2008	SpecMan Elite Verification Environment	5 Days
15-Dec-2008	Verilog Application Workshop	5 Days
18-Dec-2008	Perl Programming	2 Days

Other public courses can be scheduled as required. If you are interested in a particular course or date not shown here, please contact Esperan. We will always try our best to meet your requirements.

All courses are available as private on-site or off-site courses. Esperan can even provide pre-configured laptop training machines.

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		Esperan has been providing VHDL training and Verilog training in UK, US, Canada, Western Europe, South Africa and throughout the world.

Esperan contact information	US contact information
Phone +44 1344 865436 Fax +44 1344 865347 Email info@esperan.com	Tollfree Tel. 1800 220 8148 Fax. 1888 641 6431 Email US-sales@esperan.com