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Resources
Online information, tools and references to complement Esperan training classes.
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You may also be interested in the Esperan tutorial section - freely downloadable PDF's
on current and emerging languages and technologies.
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| General |
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| Accellera |
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| Industry-based standards organisation driving the development and enhancement of EDA
languages and techniques, such as SystemVerilog; VHDL200x; Open Verification Library.
A valuable resource for up-to-date information on the latest language developments. |
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| Deepchip |
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| John Cooley's (in)famous general EDA information site and home of the unofficial Synopsys User Group.
Great for the latest news; user reviews of EDA tools and reports from major industry conferences. |
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| Demos on Demand |
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| Chiefly a collection of online vendor tool demos, but also contains a useful tutorials section
which includes, for example, most of the tutorials, sessions and panel discussions from the last
Design Verification Conference. |
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| Open Cores |
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| Free open source IP cores and chip designs. |
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| VHDL |
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Hamburg VHDL Archive |
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| Great list of links, VHDL tools, free models, and standards documentation |
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comp.lang.vhdl FAQ
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| Frequently asked questions from the
comp.lang.vhdl newsgroup |
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Free VHDL textbook (PDF)
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| The classic free VHDL textbook from Peter Ashenden of University of Adelaide. Language coverage is
basic, but it's free and there is a full microprocessor example. Ashenden has written several
well-received books on VHDL. |
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VHDL Quickstart Lecture
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| Complementary to the above, this is a lecture on the basic concepts of VHDL, including a
suggested design flow. Available in various formats.. |
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VHDL Books by Ben Cohen
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| As well as writing books on PSL and SystemVerilog Assertions, Ben Cohen has produced a couple of
good VHDL textbooks - VHDL: Answers to FAQ is recommended for
intermediate to advanced VHDL users. |
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ESA VHDL Modelling Guidelines
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| VHDL modelling guidelines and reports from the European Space Agency |
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See also the VHDL-to-html convertor in the Tools section.
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| Verilog |
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Rajesh Bawankule's Verilog Centre |
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| Resource centre for Verilog, including alternative FAQ, links, tools documemtation. |
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comp.lang.verilog FAQ
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| Frequently asked questions from the
comp.lang.verilog newsgroup |
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Project Veripage
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| Good online Verilog, SystemVerilog and PLI tutorials, together with book links and core models. |
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See also the Verilog-to-html convertor in the Tools section.
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| SystemC |
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SystemC Homepage |
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| Home of the Open SystemC Initiative (OSCI), steering SystemC development.
Includes language reference, technical papers and download area for the SystemC reference
simulator (requires registration). |
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SystemC 2.1 Online Reference |
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| Online reference manual for the SystemC2.1 beta 11 release, built using the excellent
Doxygen documentation system
(see Tools section). |
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| TCL/TK |
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Tcl use in Synopsys |
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| Items 8 and 9 from the ESNUG download library provide useful information for
writing Tcl scripts for Synopsys tools, which use object-orientated-like
collections as data structures, instead of conventional arrays, lists or strings.
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Scripting White Paper |
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| Discusses the differences between scripting and system programming, and shows why
scripting languages (like Tcl) are better than software programming languages
(like C or Java) for gluing together tasks and applications.
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Expect Home Page |
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| Expect allows Tcl control of interactive command line programs like ftp, rlogin or telnet.
This site contains the Expect release as well as examples, papers and links. |
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