Course Structure
An optional third day for the Verification with PSL course or a standalone course for existing PSL users.
We can also offer standard or customized versions of this workshop onsite or at the location of your choice.
Course Summary
PSL Verification Units and the modeling layer
Capabilities of Verification Units; Modeling layer and its application; Flexible
verification methodologies using Verification Units; Using vunits to bind PSL or
SystemVerilog Assertion modules to legacy designs of any language.
Introduction to Formal Verification
Basics of Formal Verification; Formal Analysis terminology; Introduction to how
Formal tools work; Preparing a design for Formal Verification.
Formal Verification Methodology
Recommended approaches when using formal verification; Using a hybrid
combination of Formal verification and Simulation; Understanding the limitations of
Formal Verification. Features to define complex design protocols
Interacting FSM Case Study
How bugs escape; Generating random stimulus; Checking randomisation of stimulus;
Effects of random seed choice; Locating hard to find corner case bugs;
Effects of parameterisation;
Workshop Agenda
- Verification Units
- Types of Verification Units
- Binding
- Inheritance
- Name space (scoping) rules
- Modeling Layer
- Using PSL to improve SystemVerilog's bind command
- Introduction to Formal Verification
- Contrasting Formal and Dynamic Verification
- Formal Analysis terminology
- How Formal tools work
- State factors affecting quality of results
- Limitations of Formal Analysis tools
- Initialisation issues
- Formal Verification methodology
- Merits of Formal and Dynamic verification
- Properties in different contexts
- Getting the best return on investment in Formal
- Design Level Formal Analysis (DFLA)
- Guidelines for writing properties
- Dealing with the "size" problems
- Understanding Liveness constraints
- Parameterisation
- FSM Case Study
- Examining the verification of interacting FSM’s
- Design Description
- Verification Challenges
- Demonstrating different verification techniques
- Random Stimulus
- Concerns about randomness
- Effect of random seed choice
- Effect of parameterisation
- Parallel simulations
- Advantages of Formal Verification
- Hybrid verification
- Conclusions and Next Steps
- Index
Workshop Labs
The labs sessions include:
- Preparing a design for Formal Verification
- Debugging formal tool counter examples
- Using a Design Level Formal Analysis (DFLA) Methodology
- Writing HDL and PSL to meet a specification
- Formally verifying an HDL design containing PSL properties without simulation
- Initialisation of Formal Verification with a simulator database
Overview & booking
