What is PSL (IEEE1850)?
The Property Specification Language (PSL) is an industry and IEEE1850 standard
language for specifying design properties (assertions), functional coverage and constraints.
PSL can be embedded in HDL code and used in both simulation and Formal Verification, enabling a
sophisticated and complete Assertion Based Verification (ABV) methodology.
Find out more information on PSL with our free tutorial downloads.
Overview
Esperan’s PSL course gives you an in-depth introduction to the language,
together with guidelines and methodologies to help you create, manage and debug
effective assertions for complex design properties. The course is packed full of
examples and case studies to demonstrate real life applications of the language.
We also examine different approaches to coding assertions, including workarounds
for the restricted language support of some tools.
Duration
2 days, or 3 days in conjunction with the 1 day Advanced PSL and Formal Verification class.
We can also offer standard or customized versions of this workshop onsite or at the location of your choice.
Objectives
- To explain the advantages of Assertion Based Verification (ABV) using the Property Specification Language (PSL).
- To describe in detail the boolean, temporal, verification and modelling layers of PSL and show how the layers are used to build assertions.
- To demonstrate, with examples, good and bad PSL coding styles and show workarounds for simulators with language support issues.
- To describe, with case studies, a methodology for describing complex transaction-based assertions and properties using PSL.
Prerequisites
Delegates must be able to read, write and understand VHDL or Verilog code, and be familiar
with running and debugging HDL simulations. The workshop assumes no prior knowledge of PSL.
