Esperan - Open Verification Methodology (OVM) Training


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SystemVerilog Advanced Verification using OVM : Technical Details

Overview & booking

Course Structure
The course is based around a 5-day agenda, consisting of a 1 day Essential SystemVerilog for OVM module and a 4 day OVM library and methodology module. . These modules can be taken individually or we can also offer standard or customized versions of this course onsite or at the location of your choice.

Course Summary

Essential SystemVerilog for OVM Module
The OVM class library is quite complex, and although OVM can be used in a superficial "building-block" form, Esperan's experience is that a good background in key Object-Oriented features makes OVM easier to learn and more effective in use. This module covers essential SystemVerilog and Object-Oriented features for understanding and using OVM.

OPen Verification Methodology (OVM)
OVM is essentially a class library for SystemVerilog, which provides an infrastructure upon which a testbench can be constructed. A methodology for OVM use is implied by the structure of the library, but no explicitly specified and there are many ways of using OVM. Esperan's OVM training delivers both a description of OVM and an effective, proven methodology for it's use, based on Cadence's industry standard Universal Reuse Methodology (URM).

Course Agenda

Day 1 - Essential SystemVerilog and Object-Oriented Design

Review of Basic SystemVerilog Classes
Polymorphism and casting
Virtual Classes and Methods
Developing Robust Class Methods
Class-Based Component Hierarchy
Factory and Builder Design Patterns

Day 2 - Data, Phases and Simple Environments

Introduction to OVM Methodology

Coverage-Driven Verification
Universal Verification Component(UVC) Structure

Overview of DUT/Project
Stimulus Modeling

ovm_sequence_item
Field Automation
Data Operations (copy, clone, print etc)
Messaging
Packaging and Directory Structures

Creating a Simple Environment

Environment Topology
OVM Component Classes
Structure of a Simple Environment

OVM Simulation Phases

Phases and Co-ordination
Build & Connect Phases
Phase Initiation

Test Classes

ovm_test class
Test Selection

Day 3- Configuration, Sequences and Connections

Controlling Environment Behavior

Configuring Topology with set_config
set_config rules
Factories and Creating Data and Objects
Type and Instance Overrides

OVM Sequences
- Sequence Components
- ovm_do macros
- Complex Sequences
- Sequencer
- Built-In Sequences
- Connecting Sequencers
Connecting to a Design Under Test (DUT)

Testbenches
Virtual SystemVerilog Interfaces
Assigning Interfaces

Day 4 - Coverage and Multi-Channel Sequences

Functional Coverage Modeling

Coverage-Driven Verification
Temporal and Data Oriented Coverage
What to Cover and Where?
Covergroup Review

Interface and Module UVCs
Multi-Channel Sequences (Virtual Sequences)

Using Multi-Channel Sequences
Virtual Sequencers
Connections

Day 5 - Scoreboards and Transaction Level Modeling (TLM)

Transaction Level Modeling (TLM)

Concepts and Terminology
put, get, peek, transport, analysis
TLM fifo
Multiple ports/exports
Analysis

Building a Scoreboard
Register Modeling
Conclusions, Appendices, Index

Lab Exercises

The labs sessions include:

Creating Simple Stimulus
Simple Environments and Universal Verification Components (UVCs)
Factoies and Multiple Tests
Sequences
Integrating Multiple UVCs
Writing Multi-Channel and System-Level Tests
Building a Scoreboard

Overview & booking

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Esperan contact information	US contact information
Phone +44 1344 865436 Fax +44 1344 865347 Email info@esperan.com	Tollfree Tel. 1800 220 8148 Fax. 1888 641 6431 Email US-sales@esperan.com