OVM is the first open, interoperable, and
proven verification re-use methodology for SystemVerilog. The OVM class
library provides the basic building blocks for creating verification data and components.
When combined with an effective methodology, OVM
allows engineers to quickly develop
powerful, reusable and scalable Object-Oriented verification environments.
Overview
The course first provides essential background information on SystemVerilog classes and Object-Oriented
concepts and features. Next we describe an effective methodology for creating verification components, based on the proven
Universal Reuse Methodology (URM). The key features of the OVM class library are then examined in detail.
Finally we show how the methodology and OVM library can be combined to develop an effective verification environment.
Duration
5 days, consisting of a 1 day Essential SystemVerilog for OVM module and a
4 day OVM library and methodology module. We can also offer standard or customized versions of this course onsite or at the location of your choice.
Objectives
- To review SystemVerilog class-based features and to examine the use
of dynamic class instances to create both data objects and verification components.
- To explore the features and capabilities of the OVM class library for SystemVerilog.
- To define and explain a clear, proven methodology for creating reusable, scalable and robust verification
components.
- To gain hands-on experience of how the OVM class library can be used to implement a verification environment based on the
methodology above.
