"Much more efficient (and enjoyable) than trying to learn this stuff from a textbook"

"I'm always impressed with Esperan classes - you guys have actually USED SVA, not just knocked up a training class"

What is SystemVerilog?
SystemVerilog is a substantial set of extensions for Verilog2001, including new data types; new constructs; relaxed language rules; synthesis enhancements and powerful features to enable new verification methodologies.

What are SystemVerilog Assertions?
SystemVerilog Assertions (SVA) are a feature of SystemVerilog which allows sophisticated, multi-cycle functional checks to be embedded in [System]Verilog code as a powerful aid to design verification. SVA allows simple Verilog boolean expressions to be built into complex definitions of design behaviour, which can used for verification, functional coverage and formal verification.

This course gives you an in-depth introduction to SVA, together with guidelines and methodologies to help you create, manage and debug effective assertions for complex design properties. The course is packed full of examples, case studies and hands-on lab exercises to demonstrate real life applications of SVA. We also examine different approaches to coding assertions.

• To explain the advantages of Assertion Based Verification (ABV) using SystemVerilog Assertions (SVA).
• To describe in detail the structure of a SystemVerilog Assertion and demonstrate, with realistic examples, the full range of language features.
• To demonstrate, with examples, good and bad SVA coding styles and show design techniques for the most efficient creation of complex assertions.
  
• To describe, with case studies, a scalable methodology for reuse of SVA properties
• To describe common behaviours which SVA cannot describe and how to overcome these issues
• To explain the issues regarding verification completeness
  

2 days. We can also offer standard or customized versions of this course onsite or at the location of your choice.

Delegates must be familiar with Verilog, and with running and debugging simulations. No prior knowledge of SystemVerilog is required.

This course covers:-

SystemVerilog Assertion (SVA) Fundamentals

Explaining the benefits and issues with Assertion-Based Verification (ABV). Understanding immediate and concurrent assertions. Describing how simple boolean expressions can be built up into powerful, conditional assertions.

Sequences

Exploring SVA sequences, which allow the definition of multi-cycle design properties. Analyzing sequence design properties to understand their strength and weaknesses. Using replication and composition operators to describe complex parallel, alternate and overlapping design protocols.

Coding Guidelines and Methodologies

Demonstrating good and bad coding styles; using parameters and nesting to create compact, reusable assertions and defining a methodology for writing sophisticated assertions.

Application Issues

Exploring common behaviours that SVA alone cannot describe; describing auxiliary code and how this can be used to overcome this and other practical issues; Defining the problem of verification completeness and how this relates to capturing properties.

• Assertion Based Verification (ABV)
• Assertion Basics
  • Assertion structure
  • How to build simple assertions
  • Clocked and unclocked properties
  • Default clocks
  • Assertion placement
  • Conditional assertions (implication)
  • Overlapping evaluation
  • Using built-in functions
• Sequences
  • Sequence introduction
  • Sequential implication
  • Sequential property analysis
  • Disabling Properties
  • Cycle repetition
  • Sequence repetition
  • Analysis of repetition examples
• Sequence Composition
  • Named sequences
  • Sequence clocking
  • Overlapping and alternate sequences
  • Parallel sequences
  • throughout and within
• Advanced SVA Features
  • Evaluation of properties and assertions
  • Detecting the end of a sequence
  • Parameterized sequences and properties
  • Actions for passed or failed properties
  • Assertion variables
  • Using Expect
• Coding Guidelines and Avoiding Common Problems
  • Abstraction levels
  • Over and under constrained assertions
  • Overlapping
  • Never failing constructs
  • Assertion refinement with arbiter case study
• Coverage
  • What is coverage?
  • Structural and functional coverage
  • Coverage of the arbiter design
  • Coverage applications
• Formal Analysis Introduction
• Auxiliary Code
• Property Reuse
• Conclusions and Next Steps
• Appendices
• Index