"Verilog was a lot trickier than I expected, so the class was very useful"

There is increasing pressure on Hardware Designers to become bi-lingual. Design reuse, commercial Intellectual Property and distributed design teams are creating language neutral design methodologies, where an engineer may use SystemVerilog for writing testbenches; Verilog and VHDL for RTL design and Verilog for gate level simulation.

Verilog for VHDL is an intensive course in Verilog for engineers who already have experience of VHDL. Based on Esperan's high-quality Verilog language and application training and delivered by trainers especially chosen for their in-depth knowledge of both languages, this course is the fastest and most effective method for VHDL engineers to understand the intricacies of Verilog and become proficient in the language.
Verilog and VHDL are close enough to be familiar, but can be frustratingly different in the detail. This course will explain the key language differences. For example, in Verilog:

• Both signal and variable assignment can be made to the same object in the same process.
• Different objects are needed for the targets of concurrent and sequential assignments.
• There can be more than one case statement branch for each value in the case statement expression.
• There are only 4 logic values, but close to 200 language keywords, system tasks and compiler directives.
   

• To provide a complete understanding of the essential concepts of Verilog and how these differ from VHDL.
• To give you practical experience of writing Verilog for synthesis and verification.
• To give you the knowledge to approach your Verilog or multi-language design project with confidence.
   

The course is based around a 3-day agenda, covering language basics; synthesis coding styles and testbench creation. We can offer standard or customized versions of this course onsite or at the location of your choice.

This course assumes prior knowledge of VHDL, for example from attendance at Esperan's VHDL language and application training.

This course is structured as follows:-

Language Basics

Language concepts and constructs, including use of register versus wire types; blocking and nonblocking assignment and case statement issues.

Synthesis Coding Styles

Verilog templates for inferring combinational and registered logic, and a thorough explanation of the rules for writing high quality, reusable RTL.

Advanced Constructs and Verification Issues

Use of subprograms, compiler directives and system tasks and functions. Language techniques for testbench design are also covered.

• Verilog language introduction
  • Modules; creating hierarchy; procedures
  • Compilation; comments; identifier rules
• Data-types and Logic System
  • Logic value system; data types; net and register types
  • Vectors; literals; parameters; arrays
• Verilog Operators
• Procedural and Continuous Statements
  • Inital and always; procedural assignment; event control;
  • if and case(x|z); loops; continuous assignments;
• Procedural Statements and the Simulation Cycle
  • Blocking and non-blocking assignment; simulation cycle;
  • Event, wait and delay based timing control; timescale directive;
  • Simulation race conditions.
• Blocking and Non-Blocking Statements
  • Issues and guidelines for use of blocking/non-blocking in registered and combinational logic
• Verilog Sample Design
• RTL Rules and Guidelines
  • Rules for describing combinational and registered logic in Verilog;
  • Blocking assignment in clocked procedures
• Synthesis Coding Styles
  • State machine description;
  • if and case synthesis; parallel and full case; synthesis directives;
  • Unsupported constructs;
  • Register and latch inference issues;
• Tasks and Functions
  • Function declaration and call;
  • Task declaration and call;
  • Task issues;
• System Control
  • Compiler directives; system tasks and functions
• Using a Verilog Test Bench
  • Simple stimulus; fork and join; events;
  • Vector capture and playback; clock generation

Course Labs
The labs have been designed to follow on from each other over the course of the training, building on code developed in each lab to create an overall design project.

The lab sessions include

• Describing and verifying combinatorial logic
• Creating registered logic
• State machine design
• Verification using script driven, self-checking testbenches