| SystemVerilog for Verification |
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SystemVerilog is a huge update to Verilog, adding significant new features
and capabilities to the language. New verification features feature prominently,
with the intention of raising Verilog up the level of a dedicated High-Level
Verification Language such as Vera or e.
Such features range from minor abstraction enhancements, such as 2-state types,
through major functional additions, such as dynamic data types,
to completely new aspects for Verilog, such as Classes and functional
data coverage.
The aim of this seminar to provide a high-level overview of the key
verification features of SystemVerilog.
Agenda
- SystemVerilog overview and aims
- Verification features and enhancements
- Improved process control
- Classes and Object-Oriented Design
- Randomization
- Coverage
- Dynamic data structures
- SystemVerilog Assertions
- Open Verification Methodology (OVM)
- Summary
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| Formal Verification with SVA |
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As designs become more complex, then the verification effort increases exponentially.
Simulation times can be excessive and still not cover all input and system state scenario's.
Formal verification can mathematically and exhaustive prove a design block *always* has specified
properties for all possible combinations of inputs and system state. This is equivalent to
simulating with an infinite number of test vectors.
This webinar introduces the basic concepts and benefits of Formal Verification and the role
that SystemVerilog Assertions (SVA) plays.
The webinar will cover an introduction to Formal Verification; will contrast Simulation
and Formal verification, and show how SystemVerilog Assertions can be used to define and constrain
design behaviour.
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