Esperan – Designing with VHDL Training : Overview


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Designing with VHDL : Overview & Booking

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Overview
This four day workshop is designed for engineers who have recently learnt VHDL and who wish to learn how to create efficient hardware architectures using VHDL. This course is intended as an intensive revision of the basic concepts of digital design; an emphasis on good hardware design practices with VHDL, and an introduction to advanced methodology issues such as partitioning and asynchronous design.

This course was previously named Hardware Implementation.

Duration 4 days

Objectives

To provide a thorough review of the basic concepts and fundamental building blocks of digital design, illustrated with VHDL code examples.
To discuss the design and implementation of "medium scale" design blocks such as shifters, multipliers, dividers and Finite State Machines.
To introduce selected design methodology issues such as memory design, partitioning and asynchronous design techniques.
To teach good hardware design practices for VHDL and to reinforce the link between language constructs and synthesised hardware.

Prerequisites
Students should already have a thorough knowledge of the VHDL language, based on attending a full five day VHDL course.

DESIGNING WITH VHDL

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		Esperan has been providing VHDL training and Verilog training in UK, US, Canada, Western Europe, South Africa and throughout the world.

Esperan contact information	US contact information
Phone +44 1344 865436 Fax +44 1344 865347 Email info@esperan.com	Tollfree Tel. 1800 220 8148 Fax. 1888 641 6431 Email US-sales@esperan.com