|
Designing with VHDL : Technical Details
Course Summary
Basic Digital Design Concepts
A review of digital design building blocks, including VHDL implementation, this
section covers data formats, basic combinational and clocked building blocks,
tri-state applications and the implementation of simple arithmetic.
Designing With VHDL
The application of VHDL to the design of combinational and registered shifters; signed and unsigned
multipliers; dividers; counters and comparators. Also includes an exploration of Finite State
Machine (FSM) structuring and design options.
Design Methodology Issues
Covering memory design and implementation and partitioning guidelines, illustrated with a
complex, multi-clock domain UART example, leading into an overview of asynchronous design,
including data synchronisation, clock domain interfacing and Mean Time Between Failure (MTBF)
calculations
Workshop Agenda
- Workshop Introduction
- Definition of RTL Code (Review)
- Data Representation
- Unsigned, signed, floating
point, BCD and gray code data formats
- Combinatorial Building Blocks
- Multiplexors, decoders, encoders and priority
encoders
- Clocked Building Blocks
- Latches, flip-flops and timing characteristics of sequential circuits
- Tri-state Buses and drivers
- Tri-state devices, buses,
muxes, bus arbitration and implementation
- Arithmetic Building Blocks
- Implementation of simple addition and
subtraction
- Shifters
- Shift basics, combinational shifters, registered shifters and LFSR’s
- Synthesisable Arithmetic Packages
- Issues in using the different synthesisable arithmetic packages
- Arithmetic Implementation
- Issues in the description and synthesis
of multiplication and division
- Datapath Functions
- Organisation and types of comparators,
counters and ALUs
- State Machines
- FSM basics, structure, state
encoding and representation
- Memory structures
- Basics, synchronous and dual
port RAM, LIFO and FIFO structures
- Partitioning Issues
- Goals and rules;
synthesis partitioning; FSM partitioning
- Partitioning of a UART design
- Asynchronous Design and Metastability
- Asynchronous basics, metastability
and Mean Time Between Failure (MTBF) calculation, handling
asynchronicity, clock domain interfacing
Workshop Labs
The practical work uses paper based exercises, as well as simulator-based
labs, to relate hardware structures and VHDL code examples.
Lab sessions include :-
- Temperature Device : Data Conversion
and data arithmetic
- Quicklab: Combinational Shifter
- Quicklab: Complex Counter
|
