"Valuable verification concepts, examples and ... suggestions, combined with good open discussion"

"Great techniques for the current design ... good ideas for the next"

As ASIC and FPGA designs grow in complexity, verification is becoming the greatest challenge for completing design projects on time. To address this challenge, designers must make the most of VHDL’s capabilities, as well as adopting additional verification techniques such as Transaction Level Modeling (TLM) and Assertion Based Verification (ABV).

Esperan’s Verification with VHDL course describes specialized VHDL techniques for verification; explores essential verification technologies such as TLM and ABV; introduces complementary languages such as PSL and assesses key verification technologies such as functional coverage and formal verification.

• To make the most of VHDL’s capabilities for testbench design
• To explain key verification techniques and technologies and to understand how these complement and integrate into a VHDL verification flow.
• To introduce the Property Specification Language (PSL), which builds on VHDL syntax to enable Assertion Based Verification (ABV); functional coverage and formal verification.
• To understand the techniques you can use today, on your current project, to increase your verification efficiency.

The course is based around a 4-day agenda. We can also offer standard or customized versions of this course onsite or at the location of your choice.

Delegates should be familiar with writing and simulating VHDL, e.g. from attendance at an Esperan Master VHDL Effectively class. Some project design and verification experience is useful, but not essential.

This course covers:-

Testbench Design with VHDL

Specialized language constructs, coding techniques and methodologies for making the most of VHDL for effective testbenches and design verification.

Verification Techniques and Methodologies

Explaining techniques such as TLM, ABV and randomization, demonstrated with VHDL code, and introducing powerful verification languages such as PSL and SystemC.

Verification Technologies Overview

Pragmatic descriptions, coupled with impartial assessments, of current verification technologies, many of which are available in commercial VHDL simulators or enabled by extension languages such as PSL.

• Verification Overview
• Creating a simple test plan
• Creating a simple testbench
  • Simple stimulus
  • Test data arrays
  • File IO
• Adding self test
  • Assertion construction
  • Timing assertions
  • Hierarchical references
• Assertion Based Verification (ABV)
  • VHDL limitations
  • OVL assertion checks
  • Property Specification Language (PSL)
• Introduction to PSL
  • Foundation language
  • SERE’s
  • AMBA protocol example
• Testbench abstraction
  • Procedures and parameters
  • Stimulus procedures
  • Side-effects
• Robust procedures
  • Bus protocol procedures
  • Interrupts, timeouts, traps, early response and channels
  • Writing reusable procedures
• Transaction Level Modelling (TLM)
  • What is TLM?
  • Transactor structures
  • TLM testbench architectures
• File operations
  • EOL, EOF, comments
  • Script driven testbench
  • Dynamic file IO
  • Binary file IO
• Code Analysis
  • Linting/code purifiers
  • Static coverage metrics
  • Functional coverage
• Random stimulus
  • Pseudo-random number generators
  • Distribution control
  • Weights and constraints
• Random methodology
  • Testbench structure
  • Random test-sets
  • Directed corner cases
  • HVL randomization
• Beyond HDL
  • High-level Verification Languages (HVL)
  • C/C++ testbenches
• SystemC and IEEE1647
• SystemC Testbench
• Static Verification Methods
  • Static Timing Analysis
  • Equivalence Checking
  • Property Checking
• Putting it all together
  • Verification methodology
• Conclusions and Next Steps

Appendices:

• Simulation efficiency coding guidelines
• Dynamic data structures

Course Labs
The course labs aim to give you practical experience of testbench writing and verification tools and technologies. Some labs are tool-specific, e.g. PSL and C testbenches. Contact Esperan for details of supported tools.

The lab sessions include

• Self-checking array-based testbenches
• Simple PSL assertions
• AMBA bus Transaction Level Modeling
• Advanced ASCII and binary files
• C testbenches
• Random stimulus generation
• Dynamic data types