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What is SystemC Verification (SCV)?
SystemC is increasing being adopted for the verification of VHDL and Verilog designs and systems. However SystemC lacks some essential features for applying proven verification techniques such as randomization, Transaction Level Modeling (TLM) and dynamic resource allocation. The SystemC Verification (SCV) library is a free extension library to SystemC which enable these advanced verification techniques to be used in SystemC testbenches for HDL designs.

Esperan´s SCV course describes the background to advanced verification techniques such as Transaction Level Modeling, randomization and dynamic resource generation. The course details the features of the SCV library and demonstrates how SCV features can be used to implement these verification techniques in SystemC testbenches.
The huge productivity gains in verification which can be seen in adopting SCV make this course an absolute must for all SystemC users.

• To explain and illustrate the advantages of SCV extensions for verification; testbench design and advanced data manipulation.
• To explore the benefits of randomization techniques for verification.
• To give you a thorough background in the principles of Transaction Level Modelling (TLM) and the supporting features in SCV.
• To give you hands-on practical experience in applying SCV.

2 days. We can also offer standard or customized versions of this course onsite or at the location of your choice.

Delegates must have a good working knowledge of SystemC, e.g. by attendance on the Esperan SystemC training class. No prior knowledge of SCV is assumed.

This course covers:-

User-Defined Data Structures

Data introspection (extending user-defined data types for use with SCV transaction and randomization techniques) and advanced container classes.

Randomization

Using data randomization techniques to provide a broader spectrum of test coverage in fewer lines of code than structured stimuli.

Transaction Level Modeling (TLM)

A detailed study of TLM implementation techniques, together with modelling, recording and debugging TLM-based verification environments.

• Overview
• SystemC Verification Extensions (SCV)
• SystemC refresher
• Transaction Based Verification (TBV)
  • Transactions and transactors
  • Handling transactions
  • TBV Methodologies
• Data Introspection
  • Complex Data Types
  • Creating extensions to data objects
  • Shared & smart pointers
  • Extending user-defined types
• Randomization and Distributions
  • Overview
  • Simple randomization
  • Global seeds
  • Constraints
  • Weighted randomization
  • Weights with built-in and user-defined types
  • scv_bag with discrete values and ranges
  • Weighted constraints
  • Constraint expressions
  • Hard and soft constraints
  • Hierarchical constraints
• Transaction Recording
  • Recording concepts
  • Transaction debugging
  • Recording applications
  • SCV transaction API
  • Hierarchical transactions
• Transactor Generation
  • Generation methodology
  • Master transactor
  • Slave transactor
  • Monitor transactor
• Creating Testbenches
• Creating hierarchy and connecting HDL