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Introduction
What is SystemVerilog?
SystemVerilog is a major extension to Verilog2001, adding significant new features to Verilog for verification, design and synthesis. Enhancements range from simple new language constructs to the addition of Object-Oriented design features. There are also considerable improvements in the usability of Verilog for RTL design.
Overview
Esperan’s SystemVerilog course gives you an in-depth introduction to the main enhancements that SystemVerilog offers, discussing the benefits and issues with the new features and demonstrating how design and verification is more efficient and effective when using SystemVerilog constructs. The course breaks down into two modules. The Design module examines improvements for RTL design and synthesis; and the Verification module explores verification enhancements such as object-oriented design, assertions and randomization.
Objectives
Duration
5 days, consisting of a 2 day Design module and a 3 day Verification module. . We can also offer standard or customized versions of this course onsite or at the location of your choice.
Requirements
Delegates must be familiar with Verilog and ideally, but not essentially, Verilog2001. No prior knowledge of SystemVerilog is required.
Description
SystemVerilog Design Module
Describing the considerable enhancements for RTL design.
Topics include new data types, constructs and operators; ease-of-use improvements for procedures and subprograms; solutions for existing synthesis issues; new user-defined data types and structures; and major reforms for hierarchical connectivity such as automatic port connections, packages and interfaces.
SystemVerilog Verification Module
Exploring the major new features in SystemVerilog for writing testbenches and verifying designs.
Topics include clocking and program code blocks for testbench functionality and timing; Object-Oriented design features; functional coverage; generation of random stimuli; verification data structures; assertions and integrating C code into SystemVerilog testbenches.
This module also examines how these new features enable powerful verification techniques such as Transaction Level Modelling (TLM); Assertion-Based Verification (ABV); functional coverage and randomization of test data.
Agenda
Design Module (2 days)
Lab exercises
- Design of a simple CPU using SystemVerilog RTL constructs.
Verification Module (3 days)
- Verification of a simple CPU using SystemVerilog verification constructs.
- Using SystemVerilog features to explore Transaction Level Modelling (TLM); randomization; functional coverage and Assertion Based Verification (ABV) techniques.