"We were nervous about the Object-Oriented side, but your course and [trainer] made it seem really easy"

"Realistic labs ... great code examples"

What is the Universal Verification Methodology (UVM)?

UVM is the Accellera standard replacement for OVM (Open Verification Methodology), a class-based  verification library and reuse methodology for SystemVerilog. UVM is supported and endorsed by almost all EDA vendors, including Cadence, Mentor and Synopsys. The UVM class library provides the basic building blocks for creating verification data and components. The UVM methodology allows engineers to quickly develop powerful, reusable and scalable Object-Oriented verification environments.

UVM1.0 is virtually identical to the OVM2.1 release.
 

The course first provides essential background information on SystemVerilog classes and Object-Oriented concepts and features.

The course then describes the UVM class library which provides the building blocks and infrastructure for a verification environment, and defines a methodology to show how the class library can be used to create powerful, reusable Universal Verification Components (UVCs) based on a standard architecture. Finally we show how to combine multiple UVCs into a full verification environment.

• To review SystemVerilog class-based features and to examine the use of dynamic class instances to create both data objects and verification components.
• To explore the features and capabilities of the UVM class library for SystemVerilog.
• To define and explain a clear, proven methodology for creating reusable, scalable and robust verification components.
• To gain hands-on experience of how the UVM class library can be used to implement a verification environment based on the methodology above.

5 days, consisting of a 1 day Essential SystemVerilog for UVM module and a 4 day UVM library and methodology module. We can also offer standard or customized versions of this course onsite or at the location of your choice.

Delegates must have a good understanding of SystemVerilog. Knowledge of Object-Oriented Design with languages such as C++ or Java is advantageous, but not essential. No prior knowledge of UVM is required

Essential SystemVerilog for UVM Module

The UVM class library is quite complex, and although UVM can be used in a superficial "building-block" form, Esperan's experience is that a good background in SystemVerilog's Object-Oriented features makes UVM easier to learn and more effective in use. This module covers essential SystemVerilog and Object-Oriented features for understanding and using UVM.

Universal Verification Methodology (UVM)

UVM is essentially a class library for SystemVerilog, which provides an infrastructure upon which a testbench can be constructed. A methodology for UVM use is implied by the structure of the library, but not explicitly specified and there are many ways of using UVM. Esperan's UVM training delivers both a description of UVM and an effective, proven methodology for it's use.

UVM lab exercises are based on the verification of a real-life router design, from data description through UVC creation to multi-UVC integration, coverage and scoreboarding.

This is the key differentiator for Esperan's UVM class. It's all about the methodology. There is no point teaching all the powerful features of the class library if your engineers then struggle to create verification code. Our aim is once engineers complete this class, they can be given a verification task and will know immediately how to begin that task using UVM.

Day 1 - Essential SystemVerilog and Object-Oriented Design

• Review of Basic SystemVerilog Classes
• Polymorphism and casting
• Virtual Classes and Methods
• Developing Robust Class Methods
• Class-Based Component Hierarchy
• Factory and Builder Design Patterns

Day 2 - Data, Phases and Simple Environments

• Introduction to UVM Methodology
  • Universal Verification Component (UVC) Structure
• Overview of DUT/Project
• Stimulus Modeling
  • Declaring data items
  • Field Automation
  • Data Operations (copy, clone, print etc)
  • Messaging
  • Packaging and Directory Structures
• Creating a Simple Environment
  • UVM Simulation Phases
  • UVM Component Classes
  • Structure of a Simple Environment
  • Driver, sequencer, monitor, agent and env
• Test Classes
  • uvm_test class
  • Test Selection

Day 3- Configuration, Sequences and Connections

• Controlling Environment Behavior
  • Configuring Topology with set_config
  • set_config rules
  • Factories and Creating Data and Objects
  • Type and Instance Overrides
• UVM Sequences
  • Sequence Components
  • uvm_do macros
  • Complex Sequences
  • Objection mechanism for stopping simulation.
  • Built-In Sequences
• Connecting to a Design Under Test (DUT)
  • The Testbench layer
  • Virtual SystemVerilog Interfaces
  • Assigning Interfaces

Day 4 - Multi-Channel Sequences and Scoreboards

• Interface and Module UVCs
  • Integrating Multiple UVCs
  • UVC's with Multiple Agents
• Multi-Channel Sequences (Virtual Sequences)
  • Virtual Sequencers
  • Connections
• Building a Scoreboard
  • Scoreboard Requirements and Considerations
  • Connecting Components with TLM Analysis interfaces

Day 5 - Transaction Level Modeling (TLM) and Coverage

• Transaction Level Modeling (TLM)
  • Concepts and Terminology
  • put, get, peek, transport, analysis
  • TLM fifo
  • Multiple ports/exports
  • Analysis
• Functional Coverage Modeling
  • Coverage-Driven Verification
  • Temporal and Data Oriented Coverage
• Conclusions, Appendices, Index

Lab Exercises

Lab exercises are based around the verification of a real-life router design.

The labs sessions include:

• Creating Simple Stimulus
• Simple Environments and Universal Verification Components (UVCs)
• Factories and Multiple Tests
• Sequences
• Integrating Multiple UVCs
• Writing Multi-Channel and System-Level Tests
• Building a Scoreboard
• TLM connections
• Functional Coverage