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Testimonials
"We were nervous about the Object-Oriented side, but your course and [trainer] made it seem really easy"
"Realistic labs ... great code examples"
Introduction
What is Open Verification Methodology (OVM)?
OVM is the first open, interoperable, and proven verification re-use methodology for SystemVerilog. The OVM class library provides the basic building blocks for creating verification data and components. The OVM methodology allows engineers to quickly develop powerful, reusable and scalable Object-Oriented verification environments.
Overview
The course first provides essential background information on SystemVerilog classes and Object-Oriented concepts and features.
The course then describes the OVM class library which provides the building blocks and infrastructure for a verification environment, and defines a methodology to show how the class library can be used to create powerful, reusable Open Verification Components (OVCs) based on a standard architecture. Finally we show how to combine multiple OVCs into a full verification environment.
Objectives
Duration
5 days, consisting of a 1 day Essential SystemVerilog for OVM module and a 4 day OVM library and methodology module. We can also offer standard or customized versions of this course onsite or at the location of your choice.
Requirements
Delegates must have a good understanding of SystemVerilog. Knowledge of Object-Oriented Design with languages such as C++ or Java is advantageous, but not essential. No prior knowledge of OVM is required
Description
Essential SystemVerilog for OVM Module
The OVM class library is quite complex, and although OVM can be used in a superficial "building-block" form, Esperan's experience is that a good background in key Object-Oriented features makes OVM easier to learn and more effective in use. This module covers essential SystemVerilog and Object-Oriented features for understanding and using OVM.
Open Verification Methodology (OVM)
OVM is essentially a class library for SystemVerilog, which provides an infrastructure upon which a testbench can be constructed. A methodology for OVM use is implied by the structure of the library, but not explicitly specified and there are many ways of using OVM. Esperan's OVM training delivers both a description of OVM and an effective, proven methodology for it's use.
OVM lab exercises are based on the verification of a real-life router design, from data description through OVC creation to multi-OVC integration, coverage and scoreboarding.
Agenda
Day 1 - Essential SystemVerilog and Object-Oriented Design
Day 2 - Data, Phases and Simple Environments
Day 3- Configuration, Sequences and Connections
Day 4 - Coverage and Multi-Channel Sequences
Day 5 - Scoreboards and Transaction Level Modeling (TLM)
Lab Exercises
Lab exercises are based around the verification of a real-life router design.
The labs sessions include: