"We've been struggling to use (TLM) ourselves... But this course makes it so much easier"

"(The trainer) was very clear, and knows the subject very well"

What is Transaction Level Modeling (TLM)?
The TLM 2.0 library is the latest addition to the SystemC language. The provided set of Application Programming Interfaces have been designed to facilitate complex tasks such as: Architectural exploration; efficient modeling of complex Systems on Chip, promoting interoperability between transaction-level models from different sources as well as facilitating the integration of embedded software within the verification flow.

Esperan´s System Level Modeling with SystemC TLM 2.0 course builds on your knowledge of the SystemC language, covering the newly provided APIs and the modeling techniques used to implement Transaction Level based systems. The course will discuss the benefits and issues encountered in TLM models such as refinement, data type optimizations and communication protocols.

• Learn about the latest SystemC language features used to enable Transaction Level Modeling (TLM).
• Explore the new features of the TLM2.0 library for system level modeling and demonstrate the improvements in simulation performances and design abstraction.
• Understand the differences between the available TLM approximately-timed and loosely-timed modeling styles and how to best use them.
• Learn how to use the TLM-2.0 interfaces, sockets and payload to build fast, interoperable system level models.
• Experience how to create Transaction Level Models of common system components such as routers, arbiters, generic masters and slave modules.

2 days. We can also offer standard or customized versions of this course onsite or at the location of your choice.

Delegates must be familiar with SystemC and ideally but not essentially C++. No prior knowledge of Transaction Level Modeling techniques is required.

The course comprises 3 main sections. The Interfaces and Channels section covers a detailed study of the available building components for TLM2.0 descriptions whereas the Loosely Timed and Approximately Timed section explore modeling methods and practical examples of Transaction Level Modeling.

Interfaces and Channels

Describing the existing TLM 1.0 and TLM 2.0, structural elements, interfaces and associated channels. Topics include, definitions of blocking, non blocking, bidirectional and unidirectional interfaces; implementation of TLM channels and TLM layering principles.

Loosely Timed Modeling Style

Examining the steps involved in crafting TLM 2.0 compliant loosely timed models. Looking at practical examples of using blocking transport transactions along with time decoupling techniques. Applying design methods to improve simulation performances via direct memory interfaces.

Approximately Timed (AT) Modeling Style

Covers the requirements for TLM 2.0 compliant AT models. Illustrates the implementation of a non-blocking transport based transactions along with defined protocol requirements, memory management and transaction queues.

• Introduction to Transaction Level Modeling
  • What is TLM
  • Motivations for a TLM standard
  • Terminology
  • RTL versus TL modeling
  • TLM design methodology
• TLM Core Elements
  • SystemC based TLM
  • TLM interface implementation
  • Blocking vs non-blocking interfaces
  • Bidirectional vs unidirectional interfaces
  • Sockets, Forward and Backward interfaces
  • Direct Memory Interfaces
  • Debug transport Interfaces
• Unidirectional Interfaces
  • Unidirectional blocking interfaces
  • Blocking interfaces examples
  • Unidirectional non blocking interfaces
  • Example of non blocking interfaces
  • Convenience Interfaces
• Bidirectional Interfaces
  • Bidirectional blocking interfaces
  • Bidirectional blocking interfaces example
  • TLM 2 blocking interfaces variations
  • Loosely timed coding style
  • Global quantum and quantum keeper
  • TLM 2 blocking interfaces example
  • TLM 2 non blocking interfaces variations
  • Approximately timed coding style
  • Transaction phase and time arguments
• Standardised payload
  • The generic payload
  • Base protocol
  • Generic payload simple example
  • Generic payload advanced details
  • Generic payload use model
  • Memory management
  • Data transfer detailed example
  • Data Length
  • Data Streaming
  • Data Endianness
  • Byte enable
  • DMI hint
  • User defined payload extensions
  • Constructors and copy functions
• Memory & Debug Interfaces and Sockets
  • Combined interfaces
  • Initiator and target sockets
  • Convenience sockets and interfaces
  • Memory mapped accesses
  • Direct memory interface
  • Debug interfaces
  • Analysis interfaces and ports

Course Labs

• Lab1: Rapid platform assembly
• Lab2: Platform debug and analysis
• Lab3: Slave module creation
• Lab4: Modules basic synchronization
• Lab5: Slave access with timing
• Lab6: Channel access with timing
• Lab7: Creation of a memory controller
• Lab8: Use of an arbitrated basic channel