"Concise and complete course with practical labs"

What is SystemC?
SystemC is an open source hardware design and verification language based on C++. SystemC allows engineers to apply powerful, proven software techniques, such as object-orientated design, to the problems of system modeling and verification. Although applicable to system and hardware design, SystemC is most effective as a verification and testbench design language.

This course covers the fundamentals of SystemC, describing the features of the language and exploring how it can be used for system, hardware and verification modeling.

• To describe in detail the fundamental building blocks, data types and language constructs of SystemC
• To explain, illustrate and give you practical experience of modeling techniques using the full features of SystemC.
   

3 days. This class can also be combined with the 2 day C++ for Verification Engineers to create a 5 day SystemC course for engineers without C++ experience.

Delegates must have a good working knowledge C++, for example by attending the C++ for Verification Engineers course. Familiarity with hardware design is helpful, but not essential..

The course covers the following topics:

• Advantages and applications of system-level (especially transaction-level) modeling.
• SystemC resources, including the OSCI web site, reference manual, and other documentation.
• Creating and building SystemC netlists and hierarchical models.
• Exploring the use of different types of SystemC processes that model hardware concurrency.
• Exploring the use of SystemC primitive channels.
• Abstract interfaces and hierarchical channels for separating communication and functionality.
• Design reuse.
• Design refinement from a higher level of abstraction to a lower level of abstraction.
• Instantiate an HDL module within a SystemC design (with suitable simulator).

Fundamentals of SystemC

• SystemC Introduction
  • Scope and architecture
  • Design and simulation environment
• Language Introduction
  • Modules
  • Constructor & destructor
  • Ports and port templates
  • Channels & processes
  • Creating hierarchy
  • Makefiles
• Data Types
  • Time
  • Bit and integer types
  • Vectors
  • Strings and Characters
  • User-defined types
  • Fixed point data
• Interfaces and Channels
  • Ports and templates
  • User defined ports
  • Port and interfaces
  • Interface methods
  • Registering ports
  • Channel definitions
  • Primitive channels
  • User-defined channels
  • Channel hierarchy
  • Design example
• Processes and events
  • Processes reminder
  • Registration
  • Static sensitivity
  • Dynamic sensitivity
• Simulation
  • Time unit and resolution
  • Scheduling
  • Queues
  • Event notification
• Simulation query and control
  • Clock generation
  • Exploring a design structure
  • User defined attributes
  • Setting and retrieving attributes
  • Traversing the design hierarchy
• Debugging in SystemC
  • Trace files
  • Customizing traces
  • User-defined types
  • SystemC assertions
• SCV Overview
  • SystemC Verification library
  • CVE extensions

• C++ Reference
• NC-SystemC Design Flows