"(what I liked best about the class was) seeing synthesis results from SystemC!"

What is SystemC?
SystemC is an open source hardware design and verification language based on C++. SystemC allows engineers to apply powerful, proven software techniques, such as object-orientated design, to the problems of system modeling and verification. Although traditionally most effective as a verification language, advances in synthesis technology are now allowing direct hardware synthesis from SystemC.

This is a specialized version of the SystemC Fundamentals class for designers seeking to use SystemC with High-Level Synthesis. The emphasis is on using SystemC for hardware design rather than system-level design or verification . The course uses Cadence's C-to-Silicon compiler to explore the synthesis of SystemC code.

This course teaches SystemC from a designers viewpoint for high-level hardware synthesis using the latest generation of C to Silicon synthesis tools.

The objective is to learn SystemC for synthesis and to take a system-level SystemC design through high-level synthesis with good Quality of Results.

3 days. This class can also be combined with the 2 day C++ for Verification Engineers to create a 5 day SystemC course for Design engineers without C++ experience.

Delegates must have familiarity with digital hardware design and with C programming (for example, from attending the C++ for Verification class). A basic understanding of logic synthesis is also useful.. No prior knowledge of SystemC is required.
 

This training introduces hardware designers to high-level synthesis. It introduces them to the SystemC language; examines the SystemC coding style for high-level synthesis, and explores micro-architectural alternatives in the context of the Cadence(R) C-to-Silicon Compiler.

Day 1

• High Level Synthesis Overview
  • A brief executive-level overview of High Level Synthesis.
• SystemC Quick Introduction
  • Coding SystemC models at the RT-level.

Day 2

• Coding SystemC for High Level Synthesis
  • Preparing a system-level design for high-level synthesis.
• Case Study: Hardware Efficient Sinc Cubed Decimator
  • Demonstrates that algorithm choice affects Quality of Results.

Day 3

• Coding Tips for High Quality of Results
  • Coding your design for optimal Quality of Results (QoR).
• Synthesizing SystemC using C-to-Silicon Compiler
  • Transforming a synthesizable SystemC design to functionally-accurate Verilog RTL that meets the design specification.