"Course well structured and examples really good"

"Helped us understand the language issues and explained the solutions thoroughly"

Verilog is an HDL - a Hardware Description Language, which is used to describe electronics hardware for implementation in ASIC or FPGA devices.
 

A worldwide industry standard, Esperan's Verilog language and application training provides a thorough background in the use and application of Verilog to digital hardware design. This total training package covers all aspects of the language: from basic concepts and syntax, through synthesis coding styles and guidelines, to advanced language constructs and design verification.

• To provide a complete understanding of the essential concepts of Verilog.
• To give you practical experience of writing Verilog for synthesis and verification in a project-based environment using the latest tools.
• To give you the knowledge to approach your Verilog design project with confidence.
   

The course is based around a 5-day agenda. This can also be taken in two stages by splitting the agenda into separate 2-day Introduction and 3-day Advanced modules. We can also offer standard or customized versions of this course onsite or at the location of your choice.

Delegates should have a basic knowledge of digital hardware design and be familiar with their choice of operating system. The course assumes no prior knowledge of Verilog.

 The course covers the following:

Language Basics

The first two days of the course cover the fundamental principles of the language and the constructs most commonly used in synthesizable Register Transfer Level (RTL) design. Problematic concepts, e.g. blocking and nonblocking assignments, are discussed in depth and industry best practice guidelines presented.

Synthesis Coding Styles

The third day examines synthesis coding styles and guidelines in depth, including a thorough explanation of the rules for writing high quality, reusable syntheizable code.

Advanced Constructs and Verification Issues

Days four and five introduce further language constructs and consider techniques and strategies for the functional verification of large scale designs.

Days 1-2 Language Basics and Application Overview

• Verilog application overview
• Design objects and main language concepts
• Logic system and data types
  • Vector assignment and manipulation
  • Net, register and parameter data types
  • Choosing the correct data type
  • Memory arrays and addressing
• Operators
• Procedural statements and continuous assignments
• Procedures and timing control
• Blocking and non-blocking procedural assignments
• Conditional and loop statements
• The synthesis process and methodology overview

Day 3: Synthesis Coding Styles in Depth

• Design and verification of a simple synthesisable block
• Synthesis modeling style
  • Guidelines for combinatorial logic
  • Guidelines for synchronous logic
  • Blocking and non-blocking assignments in synthesis
• Simulation, synthesis and optimization of operators
• Coding styles for efficient hardware synthesis
  • State machine descriptions
  • Control of conditional statementsynthesis
  • Register, latch and tri-state inference

Day 4-5: Language Constructs, Coding Styles & Strategies for Verification

• Tasks and functions
  • Issues in use of tasks
• System control
  • Compiler directives
  • System tasks and functions
  • File input and output
• Coding styles and strategies for generating test stimulus
  • Design and testbench organisation
  • Stimulus generation and response capture
  • Script driven testbenches
• Structural modeling
  • Primitives and logic strength modeling
• Modeling timing
  • Delay modeling, timing checks and timing flow
• Memory Modeling
  • RAM's, ROM's and bi-directional ports
• Verilog2001 Update
  • Local declarations and initialization
  • Localparams
  • Input/output declarations
  • Subprogram enhancements
  • Array selection and assignment
  • Signed arithmetic support
  • Configurations
  • File input and output enhancements

Appendices

• User defined primitives
• Introduction to SystemVerilog
• Answers to review questions
• RTL coding templates
• Index

Course Labs
The labs have been designed to follow on from each other over the course of the course, building on code developed in each lab to create an overall design project.
The first few labs get you familiar with the tools you are using and the basic steps involved in simulating and synthesizing a small design. Subsequent labs are based upon design modeling and verification issues that are typically encountered in a real world design project.

The lab sessions include

• Familiarization with simulation and synthesis tools
• Describing and verifying combinatorial logic
• Creating registered logic
• Using vector arithmetic packages
• Structural design and hierarchy
• Verification using visualization of results
• State machine design
• Verification using script driven, self-checking testbenches
• Integration and verification of a third-party IP model